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[2001:1868:205::9]) by mx.google.com with ESMTPS id sy9si18314365pab.185.2016.06.13.08.06.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Jun 2016 08:06:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bCTQC-0005FD-9r; Mon, 13 Jun 2016 15:05:00 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bCTPC-0004Hb-7z for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2016 15:03:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 128B2707; Mon, 13 Jun 2016 08:04:19 -0700 (PDT) Received: from bc-c5-1-15.euhpc.arm.com. (bc-c5-1-15.euhpc.arm.com [10.6.16.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F324A3F253; Mon, 13 Jun 2016 08:03:37 -0700 (PDT) From: Vladimir Murzin To: linux@arm.linux.org.uk Subject: [PATCH 04/10] ARM: V7M: Add support for reading the CTR with CPUID_CACHETYPE Date: Mon, 13 Jun 2016 16:03:03 +0100 Message-Id: <1465830189-20128-5-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1465830189-20128-1-git-send-email-vladimir.murzin@arm.com> References: <1465830189-20128-1-git-send-email-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160613_080358_405513_2C7BC8AB X-CRM114-Status: GOOD ( 14.11 ) X-Spam-Score: -8.3 (--------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-8.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kernel@pengutronix.de, manabian@gmail.com, stefan@agner.ch, kbuild-all@01.org, mcoquelin.stm32@gmail.com, alexandre.torgue@gmail.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Jonathan Austin With the addition of caches to the V7M Architecture a new Cache Type Register (CTR) is defined at 0xE000ED7C. This register serves the same purpose as the V7A/R version, called CPUID_CACHETYPE in the kernel. This patch adds appropriate definitions to the cpuid macros to allow the CTR to be read with read_cpuid(reg). Signed-off-by: Jonathan Austin Signed-off-by: Vladimir Murzin --- Changelog: RFC -> v1 - use linux/io.h instead of asm/io.h (per Russell) - droped cast to void pointer in set_csselr; BASEADDR_V7M_SCB is already defined with a help of IOMEM macro (per Russell) arch/arm/include/asm/cachetype.h | 15 +++++++++++++++ arch/arm/include/asm/cputype.h | 3 ++- arch/arm/kernel/setup.c | 9 +++++---- 3 files changed, 22 insertions(+), 5 deletions(-) -- 1.7.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index 8609de8..01509ae 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -67,6 +67,7 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask) #define CSSELR_L6 (5 << 1) #define CSSELR_L7 (6 << 1) +#ifndef CONFIG_CPU_V7M static inline void set_csselr(unsigned int cache_selector) { asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector)); @@ -79,5 +80,19 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } +#else /* CONFIG_CPU_V7M */ +#include +#include "asm/v7m.h" + +static inline void set_csselr(unsigned int cache_selector) +{ + writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR); +} + +static inline unsigned int read_ccsidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); +} +#endif #endif diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index a689034..2f90cd0 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -7,7 +7,7 @@ #ifdef CONFIG_CPU_V7M #define CPUID_ID 0x0 -#define CPUID_CACHETYPE -1 +#define CPUID_CACHETYPE 0x7c #define CPUID_TCM -1 #define CPUID_TLBTYPE -1 #define CPUID_MPIDR -1 @@ -126,6 +126,7 @@ static inline unsigned int __attribute_const__ read_cpuid(unsigned offset) { switch (offset) { case CPUID_ID: + case CPUID_CACHETYPE: return readl(BASEADDR_V7M_SCB + offset); default: WARN_ON_ONCE(1); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index e414f50..3698728 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -313,11 +313,12 @@ static void __init cacheid_init(void) { unsigned int arch = cpu_architecture(); - if (arch == CPU_ARCH_ARMv7M) { - cacheid = 0; - } else if (arch >= CPU_ARCH_ARMv6) { + if (arch >= CPU_ARCH_ARMv6) { unsigned int cachetype = read_cpuid_cachetype(); - if ((cachetype & (7 << 29)) == 4 << 29) { + + if ((arch == CPU_ARCH_ARMv7M) && !cachetype) { + cacheid = 0; + } else if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ arch = CPU_ARCH_ARMv7; cacheid = CACHEID_VIPT_NONALIASING;