From patchwork Wed Aug 3 16:12:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 73224 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp939574qga; Wed, 3 Aug 2016 09:15:03 -0700 (PDT) X-Received: by 10.66.216.70 with SMTP id oo6mr116495271pac.39.1470240903328; Wed, 03 Aug 2016 09:15:03 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id lx5si9473016pab.146.2016.08.03.09.15.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Aug 2016 09:15:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUynt-0008UT-J3; Wed, 03 Aug 2016 16:13:57 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUymy-0007pb-Je for linux-arm-kernel@lists.infradead.org; Wed, 03 Aug 2016 16:13:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3EE528; Wed, 3 Aug 2016 09:14:02 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 017173F215; Wed, 3 Aug 2016 09:12:39 -0700 (PDT) From: Sudeep Holla To: Mathieu Poirier Subject: [PATCH 2/2] coresight: fix handling of ETM trace register access via sysfs Date: Wed, 3 Aug 2016 17:12:32 +0100 Message-Id: <1470240752-17331-2-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470240752-17331-1-git-send-email-sudeep.holla@arm.com> References: <1470240752-17331-1-git-send-email-sudeep.holla@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160803_091300_831561_49C5CA33 X-CRM114-Status: GOOD ( 12.77 ) X-Spam-Score: -8.3 (--------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-8.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sudeep Holla MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The ETM registers are classified into 2 categories: trace and management. The core power domain contains most of the trace unit logic including all(except TRCOSLAR and TRCOSLSR) the trace registers. The debug power domain contains the external debugger interface including all management registers. This patch adds coresight unit specific function coresight_simple_func which can be used for ETM trace registers by providing a ETM specific read function which does smp cross call to ensure the trace core is powered up before the register is accessed. Cc: Mathieu Poirier Signed-off-by: Sudeep Holla --- drivers/hwtracing/coresight/coresight-etb10.c | 2 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 2 +- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 58 ++++++++++++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 1 + drivers/hwtracing/coresight/coresight-priv.h | 9 +++- drivers/hwtracing/coresight/coresight-stm.c | 2 +- drivers/hwtracing/coresight/coresight-tmc.c | 2 +- 7 files changed, 54 insertions(+), 22 deletions(-) Hi Mathieu, I think the latest release of the firmware(inparticular SCP v1.16.0) for Juno fixes the issue you had previously encountered. However there's a pending issue with A53 ETM management register access when it's powered down. I don't think Juno platform should block these changes as ETMv4 specification is clear on the power management and register access perspective. Regards, Sudeep -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 8a4927ca9181..d7325c6534ad 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -559,7 +559,7 @@ static const struct file_operations etb_fops = { }; #define coresight_etb10_simple_func(name, offset) \ - coresight_simple_func(struct etb_drvdata, name, offset) + coresight_simple_func(struct etb_drvdata, NULL, name, offset) coresight_etb10_simple_func(rdp, ETB_RAM_DEPTH_REG); coresight_etb10_simple_func(sts, ETB_STATUS_REG); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index 02d4b629891f..4856c8098416 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -1222,7 +1222,7 @@ static struct attribute *coresight_etm_attrs[] = { }; #define coresight_etm3x_simple_func(name, offset) \ - coresight_simple_func(struct etm_drvdata, name, offset) + coresight_simple_func(struct etm_drvdata, NULL, name, offset) coresight_etm3x_simple_func(etmccr, ETMCCR); coresight_etm3x_simple_func(etmccer, ETMCCER); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 7c84308c5564..2390ee43e3d9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2039,15 +2039,38 @@ static struct attribute *coresight_etmv4_attrs[] = { NULL, }; +struct etm_reg { + void __iomem *addr; + u32 data; +}; + +static void do_smp_cross_read(void *data) +{ + struct etm_reg *reg = data; + + reg->data = readl_relaxed(reg->addr); +} + +static u32 etmv4_chk_trace_reg_access(const struct device *dev, u32 offset) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); + struct etm_reg reg; + + reg.addr = drvdata->base + offset; + smp_call_function_single(drvdata->cpu, do_smp_cross_read, ®, 1); + return reg.data; +} + #define coresight_etm4x_simple_func(name, offset) \ - coresight_simple_func(struct etmv4_drvdata, name, offset) + coresight_simple_func(struct etmv4_drvdata, NULL, name, offset) + +#define coresight_etm4x_trace_reg_func(name, offset) \ + coresight_simple_func(struct etmv4_drvdata, etmv4_chk_trace_reg_access,\ + name, offset) -coresight_etm4x_simple_func(trcoslsr, TRCOSLSR); coresight_etm4x_simple_func(trcpdcr, TRCPDCR); coresight_etm4x_simple_func(trcpdsr, TRCPDSR); coresight_etm4x_simple_func(trclsr, TRCLSR); -coresight_etm4x_simple_func(trcconfig, TRCCONFIGR); -coresight_etm4x_simple_func(trctraceid, TRCTRACEIDR); coresight_etm4x_simple_func(trcauthstatus, TRCAUTHSTATUS); coresight_etm4x_simple_func(trcdevid, TRCDEVID); coresight_etm4x_simple_func(trcdevtype, TRCDEVTYPE); @@ -2055,6 +2078,9 @@ coresight_etm4x_simple_func(trcpidr0, TRCPIDR0); coresight_etm4x_simple_func(trcpidr1, TRCPIDR1); coresight_etm4x_simple_func(trcpidr2, TRCPIDR2); coresight_etm4x_simple_func(trcpidr3, TRCPIDR3); +coresight_etm4x_trace_reg_func(trcoslsr, TRCOSLSR); +coresight_etm4x_trace_reg_func(trcconfig, TRCCONFIGR); +coresight_etm4x_trace_reg_func(trctraceid, TRCTRACEIDR); static struct attribute *coresight_etmv4_mgmt_attrs[] = { &dev_attr_trcoslsr.attr, @@ -2073,19 +2099,19 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { NULL, }; -coresight_etm4x_simple_func(trcidr0, TRCIDR0); -coresight_etm4x_simple_func(trcidr1, TRCIDR1); -coresight_etm4x_simple_func(trcidr2, TRCIDR2); -coresight_etm4x_simple_func(trcidr3, TRCIDR3); -coresight_etm4x_simple_func(trcidr4, TRCIDR4); -coresight_etm4x_simple_func(trcidr5, TRCIDR5); +coresight_etm4x_trace_reg_func(trcidr0, TRCIDR0); +coresight_etm4x_trace_reg_func(trcidr1, TRCIDR1); +coresight_etm4x_trace_reg_func(trcidr2, TRCIDR2); +coresight_etm4x_trace_reg_func(trcidr3, TRCIDR3); +coresight_etm4x_trace_reg_func(trcidr4, TRCIDR4); +coresight_etm4x_trace_reg_func(trcidr5, TRCIDR5); /* trcidr[6,7] are reserved */ -coresight_etm4x_simple_func(trcidr8, TRCIDR8); -coresight_etm4x_simple_func(trcidr9, TRCIDR9); -coresight_etm4x_simple_func(trcidr10, TRCIDR10); -coresight_etm4x_simple_func(trcidr11, TRCIDR11); -coresight_etm4x_simple_func(trcidr12, TRCIDR12); -coresight_etm4x_simple_func(trcidr13, TRCIDR13); +coresight_etm4x_trace_reg_func(trcidr8, TRCIDR8); +coresight_etm4x_trace_reg_func(trcidr9, TRCIDR9); +coresight_etm4x_trace_reg_func(trcidr10, TRCIDR10); +coresight_etm4x_trace_reg_func(trcidr11, TRCIDR11); +coresight_etm4x_trace_reg_func(trcidr12, TRCIDR12); +coresight_etm4x_trace_reg_func(trcidr13, TRCIDR13); static struct attribute *coresight_etmv4_trcidr_attrs[] = { &dev_attr_trcidr0.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 2629954429a1..ba4dd2e820ea 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -185,6 +185,7 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) +#define TRCPDSR_POWER BIT(0) /* secure state access levels */ #define ETM_EXLEVEL_S_APP BIT(8) diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index decfd52b5dc3..39841d1f58e0 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -38,14 +38,19 @@ #define ETM_MODE_EXCL_KERN BIT(30) #define ETM_MODE_EXCL_USER BIT(31) -#define coresight_simple_func(type, name, offset) \ +typedef u32 (*coresight_read_fn)(const struct device *, u32 offset); +#define coresight_simple_func(type, func, name, offset) \ static ssize_t name##_show(struct device *_dev, \ struct device_attribute *attr, char *buf) \ { \ type *drvdata = dev_get_drvdata(_dev->parent); \ + coresight_read_fn fn = func; \ u32 val; \ pm_runtime_get_sync(_dev->parent); \ - val = readl_relaxed(drvdata->base + offset); \ + if (fn) \ + val = fn(_dev->parent, offset); \ + else \ + val = readl_relaxed(drvdata->base + offset); \ pm_runtime_put_sync(_dev->parent); \ return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \ } \ diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 819629aed2f7..7949f0f6744a 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -635,7 +635,7 @@ static ssize_t traceid_store(struct device *dev, static DEVICE_ATTR_RW(traceid); #define coresight_stm_simple_func(name, offset) \ - coresight_simple_func(struct stm_drvdata, name, offset) + coresight_simple_func(struct stm_drvdata, NULL, name, offset) coresight_stm_simple_func(tcsr, STMTCSR); coresight_stm_simple_func(tsfreqr, STMTSFREQR); diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 4cbcaf93c9d9..a4748630f5d6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -218,7 +218,7 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) } #define coresight_tmc_simple_func(name, offset) \ - coresight_simple_func(struct tmc_drvdata, name, offset) + coresight_simple_func(struct tmc_drvdata, NULL, name, offset) coresight_tmc_simple_func(rsz, TMC_RSZ); coresight_tmc_simple_func(sts, TMC_STS);