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[2001:1868:205::9]) by mx.google.com with ESMTPS id i2si4137402pll.198.2017.01.06.23.13.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Jan 2017 23:13:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cPlCH-0003GL-I8; Sat, 07 Jan 2017 07:13:49 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cPlC2-0002cX-LK for linux-arm-kernel@lists.infradead.org; Sat, 07 Jan 2017 07:13:46 +0000 Received: from 172.24.1.36 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.36]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id CNR72017; Sat, 07 Jan 2017 15:07:53 +0800 (CST) Received: from localhost (10.177.23.32) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Sat, 7 Jan 2017 15:07:45 +0800 From: Ding Tianhong To: , , , , , , , , , Subject: [PATCH v7 3/4] arm64: arch_timer: Work around Erratum Hisilicon-161601 Date: Sat, 7 Jan 2017 15:07:37 +0800 Message-ID: <1483772858-10380-4-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1483772858-10380-1-git-send-email-dingtianhong@huawei.com> References: <1483772858-10380-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170106_231341_187910_7ABF137B X-CRM114-Status: GOOD ( 17.20 ) X-Spam-Score: -7.4 (-------) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-7.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.66 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.66 listed in wl.mailspike.net] 0.0 T_SPF_HELO_TEMPERROR SPF: test of HELO record failed (temperror) -3.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ding Tianhong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Erratum Hisilicon-161601 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected. The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL. The workaround is enabled if the hisilicon,erratum-161601 property is found in the timer node in the device tree. This can be overridden with the clocksource.arm_arch_timer.hisilicon-161601 boot parameter, which allows KVM users to enable the workaround until a mechanism is implemented to automatically communicate this information. Fix some description for fsl erratum a008585. Signed-off-by: Ding Tianhong --- Documentation/arm64/silicon-errata.txt | 1 + drivers/clocksource/Kconfig | 12 ++++++++- drivers/clocksource/arm_arch_timer.c | 49 ++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletion(-) -- 1.9.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 405da11..1c1a95f 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -63,3 +63,4 @@ stable kernels. | Cavium | ThunderX SMMUv2 | #27704 | N/A | | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +| Hisilicon | Hip0{5,6,7} | #161601 | HISILICON_ERRATUM_161601| diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 97f95f8..c0eabed 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -327,7 +327,7 @@ config ARM_ARCH_TIMER_EVTSTREAM config ARM_ARCH_TIMER_OOL_WORKAROUND bool "Workaround for arm arch timer unstable counter" - depends on FSL_ERRATUM_A008585 + depends on FSL_ERRATUM_A008585 || HISILICON_ERRATUM_161601 help This option would only be enabled by Freescale/NXP Erratum A-008585 or something else chip has similar erratum. @@ -343,6 +343,16 @@ config FSL_ERRATUM_A008585 value"). The workaround will only be active if the fsl,erratum-a008585 property is found in the timer node. +config HISILICON_ERRATUM_161601 + bool "Workaround for Hisilicon Erratum 161601" + default y + select ARM_ARCH_TIMER_OOL_WORKAROUND + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a workaround for Hisilicon Erratum + 161601. The workaround will be active if the hisilicon,erratum-161601 + property is found in the timer node. + config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select CLKSRC_OF if OF diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 2487c66..ef09e59f 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -131,6 +131,47 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void) } #endif +#ifdef CONFIG_HISILICON_ERRATUM_161601 +/* + * Verify whether the value of the second read is larger than the first by + * less than 32 is the only way to confirm the value is correct, so clear the + * lower 5 bits to check whether the difference is greater than 32 or not. + * Theoretically the erratum should not occur more than twice in succession + * when reading the system counter, but it is possible that some interrupts + * may lead to more than twice read errors, triggering the warning, so setting + * the number of retries far beyond the number of iterations the loop has been + * observed to take. + */ +#define __hisi_161601_read_reg(reg) ({ \ + u64 _old, _new; \ + int _retries = 50; \ + \ + do { \ + _old = read_sysreg(reg); \ + _new = read_sysreg(reg); \ + _retries--; \ + } while (unlikely((_new - _old) >> 5) && _retries); \ + \ + WARN_ON_ONCE(!_retries); \ + _new; \ +}) + +static u32 notrace hisi_161601_read_cntp_tval_el0(void) +{ + return __hisi_161601_read_reg(cntp_tval_el0); +} + +static u32 notrace hisi_161601_read_cntv_tval_el0(void) +{ + return __hisi_161601_read_reg(cntv_tval_el0); +} + +static u64 notrace hisi_161601_read_cntvct_el0(void) +{ + return __hisi_161601_read_reg(cntvct_el0); +} +#endif + #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL; EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); @@ -147,6 +188,14 @@ static u64 notrace fsl_a008585_read_cntvct_el0(void) .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, }, #endif +#ifdef CONFIG_HISILICON_ERRATUM_161601 + { + .id = "hisilicon,erratum-161601", + .read_cntp_tval_el0 = hisi_161601_read_cntp_tval_el0, + .read_cntv_tval_el0 = hisi_161601_read_cntv_tval_el0, + .read_cntvct_el0 = hisi_161601_read_cntvct_el0, + }, +#endif }; #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */