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[213.113.113.53]) by smtp.gmail.com with ESMTPSA id m18sm2314843lfe.45.2017.01.28.12.49.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 12:49:07 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Bjorn Helgaas Subject: [PATCH 4/4] ARM: dts: add PCI to the Gemini DTSI Date: Sat, 28 Jan 2017 21:48:39 +0100 Message-Id: <20170128204839.18330-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170128204839.18330-1-linus.walleij@linaro.org> References: <20170128204839.18330-1-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170128_125030_963664_6E39D032 X-CRM114-Status: GOOD ( 12.22 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.215.53 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.53 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openwrt-devel@openwrt.org, Paulius Zaleckas , linux-pci@vger.kernel.org, Linus Walleij , Janos Laube , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The Cortina Gemini has an internal PCI root bus, add this to the device tree. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Signed-off-by: Linus Walleij --- PCI maintainers: this is FYI only, I will funnel this to the ARM SoC tree once we are done with the PCI driver. --- arch/arm/boot/dts/gemini.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.9.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 405d6cedf409..df5630958038 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -99,4 +99,49 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pci@50000000 { + compatible = "cortina,gemini-pci"; + reg = <0x50000000 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */ + <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */ + <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */ + <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */ + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bus-range = <0x00 0x00>; /* Only root bus */ + /* PCI ranges mappings */ + ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + + interrupt-map-mask = <0xff00 0 0 7>; + /* + * The interrupt map is done by sub-device and per-slot. + */ + interrupt-map = <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4900 0 0 2 &pci_intc 1>, + <0x4a00 0 0 3 &pci_intc 2>, + <0x4b00 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 0>, /* Slot 10 */ + <0x5100 0 0 2 &pci_intc 1>, + <0x5200 0 0 3 &pci_intc 2>, + <0x5300 0 0 4 &pci_intc 3>, + <0x5800 0 0 1 &pci_intc 0>, /* Slot 11 */ + <0x5900 0 0 2 &pci_intc 1>, + <0x5a00 0 0 3 &pci_intc 2>, + <0x5b00 0 0 4 &pci_intc 3>, + <0x6000 0 0 1 &pci_intc 0>, /* Slot 12 */ + <0x6100 0 0 2 &pci_intc 1>, + <0x6200 0 0 3 &pci_intc 2>, + <0x6300 0 0 4 &pci_intc 3>; + pci_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; };