From patchwork Fri Aug 5 09:58:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kefeng Wang X-Patchwork-Id: 73347 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp1847532qga; Fri, 5 Aug 2016 03:01:58 -0700 (PDT) X-Received: by 10.66.83.6 with SMTP id m6mr7170234pay.80.1470391318096; Fri, 05 Aug 2016 03:01:58 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id k70si19839797pfk.85.2016.08.05.03.01.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Aug 2016 03:01:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bVbvh-0005Y1-9D; Fri, 05 Aug 2016 10:00:37 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bVbvZ-0004FM-4P for linux-arm-kernel@lists.infradead.org; Fri, 05 Aug 2016 10:00:31 +0000 Received: from 172.24.1.36 (EHLO szxeml422-hub.china.huawei.com) ([172.24.1.36]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DLI19995; Fri, 05 Aug 2016 17:59:04 +0800 (CST) Received: from [127.0.0.1] (10.177.19.180) by szxeml422-hub.china.huawei.com (10.82.67.152) with Microsoft SMTP Server id 14.3.235.1; Fri, 5 Aug 2016 17:58:54 +0800 Subject: Re: [PATCH] arm64: Support hard limit of cpu count by nr_cpus To: Will Deacon References: <1470377035-1591-1-git-send-email-wangkefeng.wang@huawei.com> <20160805083238.GA13272@arm.com> From: Kefeng Wang Message-ID: Date: Fri, 5 Aug 2016 17:58:51 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <20160805083238.GA13272@arm.com> X-Originating-IP: [10.177.19.180] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.57A4636B.017C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4ff59ee85ae6541c567cd36375bd9500 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160805_030029_598401_D6129C38 X-CRM114-Status: GOOD ( 18.54 ) X-Spam-Score: -5.6 (-----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-5.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org On 2016/8/5 16:32, Will Deacon wrote: > On Fri, Aug 05, 2016 at 02:03:55PM +0800, Kefeng Wang wrote: >> Enable the hard limit of cpu count by nr_cpus on arm64. >> The code is borrowed from MIPS. >> >> Reported-by: Shiyuan Hu >> Signed-off-by: Kefeng Wang >> --- >> arch/arm64/kernel/setup.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c >> index 536dce2..597b777 100644 >> --- a/arch/arm64/kernel/setup.c >> +++ b/arch/arm64/kernel/setup.c >> @@ -224,6 +224,21 @@ static void __init request_standard_resources(void) >> >> u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; >> >> +static void __init prefill_possible_map(void) >> +{ >> + int i, possible = num_possible_cpus(); >> + >> + if (possible > nr_cpu_ids) >> + possible = nr_cpu_ids; >> + >> + for (i = 0; i < possible; i++) >> + set_cpu_possible(i, true); >> + for (; i < NR_CPUS; i++) >> + set_cpu_possible(i, false); >> + >> + nr_cpu_ids = possible; >> +} > > Shouldn't we just avoid marking those CPUs as possible in smp_cpu_setup, > rather than rewriting things later on? How about this one, >From 0965eebecbc5aea0473df0cb45d32b2fccf72a9a Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Fri, 5 Aug 2016 17:44:33 +0800 Subject: [PATCH v2] arm64: Support hard limit of cpu count by nr_cpus Enable the hard limit of cpu count by set boot options nr_cpus=x on arm64. Signed-off-by: Kefeng Wang --- arch/arm64/kernel/smp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 1.7.12.4 > > Also, can you explain exactly what functionality is missing at the moment, > please? I assume it's the nr_cpus= option not working correctly? Yes. they use same bootargs nr_cpus=1 on both arm64 and x86, but find it can't work in arm64. > > Will > > . > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 76a6d92..0ac3ff5 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -496,7 +496,10 @@ static int __init smp_cpu_setup(int cpu) if (cpu_ops[cpu]->cpu_init(cpu)) return -ENODEV; - set_cpu_possible(cpu, true); + if (cpu < nr_cpu_ids) + set_cpu_possible(cpu, true); + else + return -EINVAL; return 0; }