From patchwork Wed Jul 6 14:40:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 588237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66B03CCA47F for ; Wed, 6 Jul 2022 14:40:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233075AbiGFOkt (ORCPT ); Wed, 6 Jul 2022 10:40:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232713AbiGFOkt (ORCPT ); Wed, 6 Jul 2022 10:40:49 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 939671BEB1; Wed, 6 Jul 2022 07:40:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657118448; x=1688654448; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=HFOIH+wGXMPcjUrkZQW9tzLiSkOeVQaMCor9sLUlCKI=; b=pz2VJRNnrhaGv4pKSkZr9R1d4gNY4/dQhQWvITZl3Bei0wY5ZiqpaI97 2PoHJpN49zg6/vyVFD0gXr2wJ4OUMHTyst7OHGqj8SJhsNdypZdT4iXtT dexK/Vq8n0Hh8w4N+aHzpva5M44aWtTL+0SVyAemt2EVxlpFkCmBMGQNx 0=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 06 Jul 2022 07:40:48 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 06 Jul 2022 07:40:47 -0700 X-QCInternal: smtphost Received: from hu-krichai-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.110.37]) by ironmsg02-blr.qualcomm.com with ESMTP; 06 Jul 2022 20:10:27 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 6110942A1; Wed, 6 Jul 2022 20:10:26 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Krishna chaitanya chundru Subject: [PATCH v4 0/2] PCI: Restrict pci transactions after pci suspend Date: Wed, 6 Jul 2022 20:10:23 +0530 Message-Id: <1657118425-10304-1-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656684800-31278-1-git-send-email-quic_krichai@quicinc.com> References: <1656684800-31278-1-git-send-email-quic_krichai@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the endpoint device state is D0 and irq's are not freed, then kernel try to mask interrupts in system suspend path by writing in to the vector table (for MSIX interrupts) and config space (for MSI's). These transactions are initiated in the pm suspend after pcie clocks got disabled as part of platform driver pm suspend call. Due to it, these transactions are resulting in un-clocked access and eventually to crashes. So added a logic in qcom driver to restrict these unclocked access. And updated the logic to check the link state before masking or unmasking the interrupts. Krishna chaitanya chundru (2): PCI: qcom: Add system PM support PCI: qcom: Restrict pci transactions after pci suspend drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++- drivers/pci/controller/dwc/pcie-qcom.c | 121 +++++++++++++++++++++- 2 files changed, 131 insertions(+), 4 deletions(-)