[v4,0/3] Add devicetree support of Interconnects and USB for SDX75

Hi,

Changes in v4:
 - Reordered the interconnect to keep it in sorted order in patch 1/3.

Changes in v3:
 - Using macro QCOM_ICC_TAG_ALWAYS instead of 0 in interconnects properties.
 - Collected reviewed by tag.

Changes in v2:
 - Updated the commit subject of patch 2/3.

This series adds devicetree nodes to support interconnects and usb for sdx75.
This is based on previously sent driver series[1], [2].

[1] https://lore.kernel.org/all/1694614256-24109-1-git-send-email-quic_rohiagar@quicinc.com/
[2] https://lore.kernel.org/all/1695359525-4548-1-git-send-email-quic_rohiagar@quicinc.com/

Thanks,
Rohit.

Rohit Agarwal (3):
  arm64: dts: qcom: Add interconnect nodes for SDX75
  arm64: dts: qcom: Add USB3 and PHY support on SDX75
  arm64: dts: qcom: sdx75-idp: Enable USB3 and PHY support

 arch/arm64/boot/dts/qcom/sdx75-idp.dts |  29 ++++++
 arch/arm64/boot/dts/qcom/sdx75.dtsi    | 170 +++++++++++++++++++++++++++++++++
 2 files changed, 199 insertions(+)

On 10/4/23 10:08, Rohit Agarwal wrote:
> Add interconnect nodes to support interconnects on SDX75.
> Also parallely add the interconnect property for UART required
> so that the bootup to shell does not break with interconnects
> in place.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 52 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> index e180aa4..b4723fa 100644
> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> @@ -8,6 +8,8 @@
>   
>   #include <dt-bindings/clock/qcom,rpmh.h>
>   #include <dt-bindings/clock/qcom,sdx75-gcc.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,sdx75.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/power/qcom,rpmhpd.h>
>   #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -203,6 +205,19 @@
>   		};
>   	};
>   
> +	clk_virt: interconnect-0 {
> +		compatible = "qcom,sdx75-clk-virt";
> +		#interconnect-cells = <2>;
> +		qcom,bcm-voters = <&apps_bcm_voter>;
> +		clocks = <&rpmhcc RPMH_QPIC_CLK>;
> +	};
> +
> +	mc_virt: interconnect-1 {
> +		compatible = "qcom,sdx75-mc-virt";
> +		#interconnect-cells = <2>;
> +		qcom,bcm-voters = <&apps_bcm_voter>;
> +	};
> +
>   	memory@80000000 {
>   		device_type = "memory";
>   		reg = <0x0 0x80000000 0x0 0x0>;
> @@ -434,6 +449,9 @@
>   			clock-names = "m-ahb",
>   				      "s-ahb";
>   			iommus = <&apps_smmu 0xe3 0x0>;
> +			interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
> +					 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
> +			interconnect-names = "qup-core";
No qup-config?

My brain compiler says this would cause a dt checker warning, at least 
on next-20231012.

Konrad

On 10/12/23 18:57, Rohit Agarwal wrote:
> 
> On 10/12/2023 10:18 PM, Konrad Dybcio wrote:
>>
>>
>> On 10/4/23 10:08, Rohit Agarwal wrote:
>>> Add interconnect nodes to support interconnects on SDX75.
>>> Also parallely add the interconnect property for UART required
>>> so that the bootup to shell does not break with interconnects
>>> in place.
>>>
>>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 
>>> +++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 52 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi 
>>> b/arch/arm64/boot/dts/qcom/sdx75.dtsi
>>> index e180aa4..b4723fa 100644
>>> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
>>> @@ -8,6 +8,8 @@
>>>     #include <dt-bindings/clock/qcom,rpmh.h>
>>>   #include <dt-bindings/clock/qcom,sdx75-gcc.h>
>>> +#include <dt-bindings/interconnect/qcom,icc.h>
>>> +#include <dt-bindings/interconnect/qcom,sdx75.h>
>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>   #include <dt-bindings/power/qcom,rpmhpd.h>
>>>   #include <dt-bindings/power/qcom-rpmpd.h>
>>> @@ -203,6 +205,19 @@
>>>           };
>>>       };
>>>   +    clk_virt: interconnect-0 {
>>> +        compatible = "qcom,sdx75-clk-virt";
>>> +        #interconnect-cells = <2>;
>>> +        qcom,bcm-voters = <&apps_bcm_voter>;
>>> +        clocks = <&rpmhcc RPMH_QPIC_CLK>;
>>> +    };
>>> +
>>> +    mc_virt: interconnect-1 {
>>> +        compatible = "qcom,sdx75-mc-virt";
>>> +        #interconnect-cells = <2>;
>>> +        qcom,bcm-voters = <&apps_bcm_voter>;
>>> +    };
>>> +
>>>       memory@80000000 {
>>>           device_type = "memory";
>>>           reg = <0x0 0x80000000 0x0 0x0>;
>>> @@ -434,6 +449,9 @@
>>>               clock-names = "m-ahb",
>>>                         "s-ahb";
>>>               iommus = <&apps_smmu 0xe3 0x0>;
>>> +            interconnects = <&clk_virt MASTER_QUP_CORE_0 
>>> QCOM_ICC_TAG_ALWAYS
>>> +                     &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
>>> +            interconnect-names = "qup-core";
>> No qup-config?
>>
>> My brain compiler says this would cause a dt checker warning, at least 
>> on next-20231012.
> If I check the tip, then there is only one interconnect entry.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/soc/qcom/qcom%2Cgeni-se.yaml#L50
> For the debug uart, the qup-config is added.
> I did check the dtbs_check before sending these patches.
> Please let me know if I am missing anything.
Oh, my brain compiler was correct, but for the wrong input data :)

I thought you added this property to the UART itself, not to the QUP 
controller. Yes, you're right.

Konrad