From patchwork Mon May 4 20:22:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 189299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EF67C3A5A9 for ; Mon, 4 May 2020 20:24:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 442D920721 for ; Mon, 4 May 2020 20:24:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="foRm2c2Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726404AbgEDUYD (ORCPT ); Mon, 4 May 2020 16:24:03 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:60764 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726111AbgEDUYD (ORCPT ); Mon, 4 May 2020 16:24:03 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1588623843; h=Content-Transfer-Encoding: MIME-Version: Message-Id: Date: Subject: Cc: To: From: Sender; bh=HTXjWdBLrHj7qKXU26YhsxMP+8VY0C42SPBv+HCFlE4=; b=foRm2c2ZYnq/kPLuyV+ZHh97aSmKmLPJJloy/gvI46e+w/7K5M0ReVFP8jXtoJfNuA4kyQk/ 7a6O8oPrI0lD3ki3r/j3B9UT8/vFHpu4FDzcpnbMGqVMKfEncT1KbYpxHO3VGHd1v9Cnk3CW wySyiTkVXm6jR7wn3pid+rBJ4xw= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5eb079cd.7f8bed75ba08-smtp-out-n05; Mon, 04 May 2020 20:23:41 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 82689C44788; Mon, 4 May 2020 20:23:39 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6780DC433CB; Mon, 4 May 2020 20:23:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6780DC433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, bjorn.andersson@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, Sibi Sankar Subject: [PATCH v4 00/12] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Date: Tue, 5 May 2020 01:52:31 +0530 Message-Id: <20200504202243.5476-1-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch series aims to extend cpu based scaling support to L3/DDR on SDM845 and SC7180 SoCs. Patches [1-3] - Blacklist SDM845 and SC7180 in cpufreq-dt-platdev Patches [4-8] - Update bw levels based on cpu frequency change Patches [9-10] - Add tag setting support to OPP Patches [11-12] - Add the cpu opp tables for SDM845 and SC7180 SoCs. Depends on the following series: https://lore.kernel.org/patchwork/cover/1230626/ Georgi, Would it make sense to include tag support patches [9-10] in your next re-spin? V4: * Migrate to using Georgi's new bindings * Misc fixups based on Matthias comments * API fixups based on Bjorn's comments on v2 * Picked up a few R-bs from Matthias v3: * Migrated to using Saravana's opp-kBps bindings [1] * Fixed some misc comments from Rajendra * Added support for SC7180 v2: * Incorporated Viresh's comments from: https://lore.kernel.org/lkml/20190410102429.r6j6brm5kspmqxc3@vireshk-i7/ https://lore.kernel.org/lkml/20190410112516.gnh77jcwawvld6et@vireshk-i7/ * Dropped cpufreq-map passive governor Sibi Sankar (12): arm64: dts: qcom: sdm845: Add SoC compatible to MTP cpufreq: blacklist SDM845 in cpufreq-dt-platdev cpufreq: blacklist SC7180 in cpufreq-dt-platdev OPP: Add and export helper to update voltage OPP: Add and export helper to set bandwidth cpufreq: qcom: Update the bandwidth levels on frequency change OPP: Add and export helper to get icc path count cpufreq: qcom: Disable fast switch when scaling ddr/l3 dt-bindings: interconnect: Add interconnect-tags bindings OPP: Add support for setting interconnect-tags arm64: dts: qcom: sdm845: Add cpu OPP tables arm64: dts: qcom: sc7180: Add cpu OPP tables .../bindings/interconnect/interconnect.txt | 5 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 168 ++++++++++++ arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 258 ++++++++++++++++++ drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/qcom-cpufreq-hw.c | 89 +++++- drivers/opp/core.c | 114 ++++++++ drivers/opp/of.c | 25 +- include/linux/pm_opp.h | 22 ++ 9 files changed, 675 insertions(+), 10 deletions(-) Reported-by: Sibi Sankar Signed-off-by: Viresh Kumar