| Message ID | 20201119072714.14460-1-manivannan.sadhasivam@linaro.org |
|---|---|
| Headers | show |
| Series | Add GCC and RPMh clock support for SDX55 | expand |
Quoting Manivannan Sadhasivam (2020-11-18 23:27:11) > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > new file mode 100644 > index 000000000000..9d8981817ae3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > @@ -0,0 +1,73 @@ [...] > + > +properties: > + compatible: > + const: qcom,gcc-sdx55 > + > + clocks: > + items: [...] > + - description: PLL test clock source > + > + clock-names: > + items: [...] > + - const: core_bi_pll_test_se Is it optional? As far as I know this clk has never been implemented because it's a hardware validation thing and not used otherwise.
On 25 November 2020 7:44:10 AM IST, Stephen Boyd <sboyd@kernel.org> wrote: >Quoting Manivannan Sadhasivam (2020-11-18 23:27:11) >> diff --git >a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml >b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml >> new file mode 100644 >> index 000000000000..9d8981817ae3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml >> @@ -0,0 +1,73 @@ >[...] >> + >> +properties: >> + compatible: >> + const: qcom,gcc-sdx55 >> + >> + clocks: >> + items: >[...] >> + - description: PLL test clock source >> + >> + clock-names: >> + items: >[...] >> + - const: core_bi_pll_test_se > >Is it optional? As far as I know this clk has never been implemented >because it's a hardware validation thing and not used otherwise. It is implemented in drivers but not used as you said. But since it is the parent clk of PLLs I'm not sure we can make it optional. Thanks, Mani -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
Quoting Manivannan Sadhasivam (2020-11-24 19:49:24) > > > On 25 November 2020 7:44:10 AM IST, Stephen Boyd <sboyd@kernel.org> wrote: > >Quoting Manivannan Sadhasivam (2020-11-18 23:27:11) > >> diff --git > >a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > >b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > >> new file mode 100644 > >> index 000000000000..9d8981817ae3 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > >> @@ -0,0 +1,73 @@ > >[...] > >> + > >> +properties: > >> + compatible: > >> + const: qcom,gcc-sdx55 > >> + > >> + clocks: > >> + items: > >[...] > >> + - description: PLL test clock source > >> + > >> + clock-names: > >> + items: > >[...] > >> + - const: core_bi_pll_test_se > > > >Is it optional? As far as I know this clk has never been implemented > >because it's a hardware validation thing and not used otherwise. > > It is implemented in drivers but not used as you said. But since it is the parent clk of PLLs I'm not sure we can make it optional. We can leave it out completely if the bootloader code never uses it as a parent of the PLL. That scenario would be pretty weird and is why we removed it from the video clk controller in commit abc8f93f33e7 ("clk: qcom: Get rid of the test clock for videocc-sc7180"). I'm fine if you want to keep it, but I'm confused why you care so much :)