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[v1,0/3] Add USB HS support for SM4250/6115

Message ID 20210622203240.559979-1-iskren.chernev@gmail.com
Headers show
Series Add USB HS support for SM4250/6115 | expand

Message

Iskren Chernev June 22, 2021, 8:32 p.m. UTC 
The USB controller found on SM4250/6115 is dwc3 (phy v1), very similar to
existing supported phys (like msm8996), with slighly different tune seq.

Iskren Chernev (3):
  dt-bindings: usb: qcom,dwc3: Add bindings for sm6115/4250
  dt-bindings: phy: qcom,qusb2: document sm4250/6115 compatible
  phy: qcom-qusb2: Add configuration for SM4250 and SM6115

 .../bindings/phy/qcom,qusb2-phy.yaml          |  2 ++
 .../devicetree/bindings/usb/qcom,dwc3.yaml    |  2 ++
 drivers/phy/qualcomm/phy-qcom-qusb2.c         | 34 +++++++++++++++++++
 3 files changed, 38 insertions(+)


base-commit: e71e3a48a7e89fa71fb70bf4602367528864d2ff
--
2.31.1

Comments

Bjorn Andersson June 23, 2021, 3:33 a.m. UTC | #1 
On Tue 22 Jun 15:32 CDT 2021, Iskren Chernev wrote:

> Add the compatible string for SM6115/4250 SoC from Qualcomm.
> 
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index 413299b5fe2b..4e6451789806 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -19,6 +19,8 @@ properties:
>            - qcom,sc7280-dwc3
>            - qcom,sdm845-dwc3
>            - qcom,sdx55-dwc3
> +          - qcom,sm4250-dwc3
> +          - qcom,sm6115-dwc3
>            - qcom,sm8150-dwc3
>            - qcom,sm8250-dwc3
>            - qcom,sm8350-dwc3
> -- 
> 2.31.1
>
Bjorn Andersson June 23, 2021, 3:37 a.m. UTC | #2 
On Tue 22 Jun 15:32 CDT 2021, Iskren Chernev wrote:

> The SM4250 and SM6115 uses the same register layout as MSM8996, but the

> tune sequence is a bit different.

> 


Didn't review the initialization sequence, but it's different from the
existing ones so adding a new compatible and init_tbl seems to be the
right choice.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>


Regards,
Bjorn

> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>

> ---

>  drivers/phy/qualcomm/phy-qcom-qusb2.c | 34 +++++++++++++++++++++++++++

>  1 file changed, 34 insertions(+)

> 

> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c

> index 8f1bf7e2186b..3c1d3b71c825 100644

> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c

> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c

> @@ -219,6 +219,22 @@ static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {

>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),

>  };

>  

> +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {

> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),

> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),

> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),

> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),

> +

> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),

> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),

> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),

> +

> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),

> +

> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),

> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),

> +};

> +

>  static const unsigned int qusb2_v2_regs_layout[] = {

>  	[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,

>  	[QUSB2PHY_PLL_STATUS]		= 0x1a0,

> @@ -342,6 +358,18 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {

>  	.autoresume_en	 = BIT(3),

>  };

>  

> +static const struct qusb2_phy_cfg sm6115_phy_cfg = {

> +	.tbl		= sm6115_init_tbl,

> +	.tbl_num	= ARRAY_SIZE(sm6115_init_tbl),

> +	.regs		= msm8996_regs_layout,

> +

> +	.has_pll_test	= true,

> +	.se_clk_scheme_default = true,

> +	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),

> +	.mask_core_ready = PLL_LOCKED,

> +	.autoresume_en	 = BIT(3),

> +};

> +

>  static const char * const qusb2_phy_vreg_names[] = {

>  	"vdda-pll", "vdda-phy-dpdm",

>  };

> @@ -888,6 +916,12 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {

>  	}, {

>  		.compatible	= "qcom,sdm660-qusb2-phy",

>  		.data		= &sdm660_phy_cfg,

> +	}, {

> +		.compatible	= "qcom,sm4250-qusb2-phy",

> +		.data		= &sm6115_phy_cfg,

> +	}, {

> +		.compatible	= "qcom,sm6115-qusb2-phy",

> +		.data		= &sm6115_phy_cfg,

>  	}, {

>  		/*

>  		 * Deprecated. Only here to support legacy device

> -- 

> 2.31.1

>
Iskren Chernev June 25, 2021, 10:38 a.m. UTC | #3 
On 6/23/21 6:37 AM, Bjorn Andersson wrote:
> On Tue 22 Jun 15:32 CDT 2021, Iskren Chernev wrote:
> 
>> The SM4250 and SM6115 uses the same register layout as MSM8996, but the
>> tune sequence is a bit different.
>>
> 
> Didn't review the initialization sequence, but it's different from the
> existing ones so adding a new compatible and init_tbl seems to be the
> right choice.

Here is the init sequence I'm using [1]

[1] https://github.com/OnePlusOSS/android_kernel_oneplus_sm4250/blob/oneplus/SM4250_Q_10.0/arch/arm64/boot/dts/vendor/20882/bengal-qrd.dtsi#L130

> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> Regards,
> Bjorn
> 
>> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
>> ---
>>  drivers/phy/qualcomm/phy-qcom-qusb2.c | 34 +++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index 8f1bf7e2186b..3c1d3b71c825 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -219,6 +219,22 @@ static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
>>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
>>  };
>>  
>> +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
>> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
>> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
>> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),
>> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),
>> +
>> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
>> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
>> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
>> +
>> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
>> +
>> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
>> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
>> +};
>> +
>>  static const unsigned int qusb2_v2_regs_layout[] = {
>>  	[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
>>  	[QUSB2PHY_PLL_STATUS]		= 0x1a0,
>> @@ -342,6 +358,18 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
>>  	.autoresume_en	 = BIT(3),
>>  };
>>  
>> +static const struct qusb2_phy_cfg sm6115_phy_cfg = {
>> +	.tbl		= sm6115_init_tbl,
>> +	.tbl_num	= ARRAY_SIZE(sm6115_init_tbl),
>> +	.regs		= msm8996_regs_layout,
>> +
>> +	.has_pll_test	= true,
>> +	.se_clk_scheme_default = true,
>> +	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
>> +	.mask_core_ready = PLL_LOCKED,
>> +	.autoresume_en	 = BIT(3),
>> +};
>> +
>>  static const char * const qusb2_phy_vreg_names[] = {
>>  	"vdda-pll", "vdda-phy-dpdm",
>>  };
>> @@ -888,6 +916,12 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
>>  	}, {
>>  		.compatible	= "qcom,sdm660-qusb2-phy",
>>  		.data		= &sdm660_phy_cfg,
>> +	}, {
>> +		.compatible	= "qcom,sm4250-qusb2-phy",
>> +		.data		= &sm6115_phy_cfg,
>> +	}, {
>> +		.compatible	= "qcom,sm6115-qusb2-phy",
>> +		.data		= &sm6115_phy_cfg,
>>  	}, {
>>  		/*
>>  		 * Deprecated. Only here to support legacy device
>> -- 
>> 2.31.1
>>