From patchwork Wed Mar 2 20:30:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 547643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DE90C433FE for ; Wed, 2 Mar 2022 20:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243383AbiCBUbm (ORCPT ); Wed, 2 Mar 2022 15:31:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243400AbiCBUbl (ORCPT ); Wed, 2 Mar 2022 15:31:41 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAB52CE916 for ; Wed, 2 Mar 2022 12:30:57 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id cx5so2826846pjb.1 for ; Wed, 02 Mar 2022 12:30:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6sWy4/TaV/KEk/+p6c6dVcypbRzCQ7sFtzJvPWQsaOI=; b=KkDF9fD1aWCQdGpFKtwwZbjnDIO8irQgmjEl86HZtZdrvvngBzTN4etG/0Ri6EF8W6 gMjaGwx6mPFE5tvqtCqNgypumEuw2QZAD1N1642E59+v5ByGHPhGH9lJ2zM90ouUK6cP mk2zIxUhix+67Y2g2+1ne7sR8OZKJouX1rkVUKxSjKCsMdF82c3fkR6/9Zh7LfOzsQnX DbNCC0SJOO7393Hbq8y+A1jATFLitQBiF6Qx6DQlGrEWo6fOf3wE2u/d4ao1OHl9bLR6 pQNuJIuZNbiUsmX5wNg4bIx7V17TyPm2TZ/aXgoUYSGzHg6dio+V6cOGs3i8dqWocvz/ VCxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6sWy4/TaV/KEk/+p6c6dVcypbRzCQ7sFtzJvPWQsaOI=; b=XFN6mwl6Ir7jn7knFHzIJoRpEYsghR5nm8aRtq5YQCj9GNL35sg7fx0mn86aJk6DOe O8+SHJmGfi2U5X+Sg4KjjDj7vIo9MPy5jHU1lZ2hktXfTqdm2gsp819A1r0afV5FKQXd nv5Bz2kVzZ9PGXILGdkZf26/Nxkx3ng0RyBnnm7hzRAMFzyaUE4hwTmp64bEa32BLmxI GM6IHQmi+ufCeePKsjGdOg3+98atzTeA+4gUEttZdSn3FKL/zLsLBjsc8UFvCL6ijJh1 MYBkQ4d6O9fXVxv6IzIpGwOfgzY7eMCH2JUfEmQ/Qn7BqrII40F3Naa0S+l6wBMbW3ZZ wvSg== X-Gm-Message-State: AOAM5320xPREfzJDowOy7705bIAScwHBz8Xu82/LTLD3Jyh3i3W7RIHY qZFZCzX28X4VyfX2qrJYkJOLLGLNuZiW3A== X-Google-Smtp-Source: ABdhPJwTwrT5eJMRvTA9IudLJVLqPucmAFpRbgQ3mbKPzWCx3jJcKSGaUJR72m8GCOdOi3JHdtzcYw== X-Received: by 2002:a17:90a:d90b:b0:1bc:4ec7:d867 with SMTP id c11-20020a17090ad90b00b001bc4ec7d867mr1596549pjv.226.1646253056940; Wed, 02 Mar 2022 12:30:56 -0800 (PST) Received: from localhost.localdomain ([182.64.85.91]) by smtp.gmail.com with ESMTPSA id b1-20020a17090aa58100b001bcb7bad374sm5963410pjq.17.2022.03.02.12.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:30:56 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org Subject: [PATCH v3 0/7] Add PCIe support for SM8150 SoC Date: Thu, 3 Mar 2022 02:00:38 +0530 Message-Id: <20220302203045.184500-1-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Changes since v2: ----------------- - v2 can be found here: https://lore.kernel.org/linux-arm-msm/20220301072511.117818-1-bhupesh.sharma@linaro.org/T/ - Fixed review comments from Dmitry and Bjorn. - Modified [PATCH 3/7] from v1 to include gdsc driver structs and support code for PCIe0 and PCIe1 (in addition to defines for the same). Changes since v1: ----------------- - v1 can be found here: https://lore.kernel.org/linux-arm-msm/20220223192946.473172-1-bhupesh.sharma@linaro.org/T/ - Collected ACKs on [PATCH 1/7], [PATCH 2/7] and [PATCH 4/7] from Rob and Dmitry. - Broke down another separately sent out PATCH (see [1]), into a 3 patches (one each for emac, pci and ufs gdsc defines) - one of which is carried as [PATCH 3/7] in this series, which fixes a compilation error. The rest of the gdsc defines have been sent out as separate patch(es). [1]. https://patchwork.kernel.org/project/netdevbpf/patch/20220126221725.710167-4-bhupesh.sharma@linaro.org/ - Rob's bot reported a number of 'dtbs_check' errors with the v1 series, which are been fixed with a separate series now (see [2]), to ease the review of this series. [2]. https://lore.kernel.org/linux-arm-msm/20220228123019.382037-1-bhupesh.sharma@linaro.org/T/ This series adds PCIe support for Qualcomm SM8150 SoC with relevant PHYs. There are 2 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly compatible with the ones found on SM8250 SoC, hence the old drivers are modified to add the support. This series has been tested on SA8155p ADP board with QCA6696 chipset connected onboard. Cc: Bjorn Andersson Cc: Rob Herring Bhupesh Sharma (7): dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 phy: qcom-qmp: Add SM8150 PCIe QMP PHYs PCI: qcom: Add SM8150 SoC support arm64: dts: qcom: sm8150: Add PCIe nodes arm64: dts: qcom: sa8155: Enable PCIe nodes .../devicetree/bindings/pci/qcom,pcie.txt | 5 +- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 + arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 +++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 ++++++++++++++++++ drivers/clk/qcom/gcc-sm8150.c | 20 ++ drivers/pci/controller/dwc/pcie-qcom.c | 8 + drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 + 8 files changed, 412 insertions(+), 2 deletions(-)