| Message ID | 20220602133039.1739490-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | drm/msm: clean up the hw catalog init | expand |
On 6/2/2022 6:30 AM, Dmitry Baryshkov wrote: > Rather than checking hwversion, follow the usual patter and add special > bit to the lm->features to check whether the LM has combined or separate > alpha registers. While we are at it, rename > dpu_hw_lm_setup_blend_config_sdm845() to > dpu_hw_lm_setup_blend_config_combined_alpha(). > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 17 ++++++++++------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- > 3 files changed, 15 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 400ebceb56bb..78c7d987c2ca 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -50,9 +50,12 @@ > #define DMA_CURSOR_MSM8998_MASK \ > (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) > > -#define MIXER_SDM845_MASK \ > +#define MIXER_MSM8998_MASK \ > (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) > > +#define MIXER_SDM845_MASK \ > + (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) > + > #define MIXER_SC7180_MASK \ > (BIT(DPU_DIM_LAYER)) > > @@ -936,17 +939,17 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = { > }; > > static const struct dpu_lm_cfg msm8998_lm[] = { > - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, > + LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, > &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), > - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, > + LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, > &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), > - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, > + LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, > &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), > - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, > + LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, > &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), > - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, > + LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, > &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), > - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, > + LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, > &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 8cb6d1f25bf9..80bc09b1f1b3 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -145,6 +145,7 @@ enum { > * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration > * @DPU_MIXER_GC Gamma correction block > * @DPU_DIM_LAYER Layer mixer supports dim layer > + * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register > * @DPU_MIXER_MAX maximum value > */ > enum { > @@ -152,6 +153,7 @@ enum { > DPU_MIXER_SOURCESPLIT, > DPU_MIXER_GC, > DPU_DIM_LAYER, > + DPU_MIXER_COMBINED_ALPHA, > DPU_MIXER_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > index 462f5082099e..25d2eba28e71 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > @@ -148,7 +148,7 @@ static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) > return 0; > } > > -static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, > +static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx, > u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) > { > struct dpu_hw_blk_reg_map *c = &ctx->hw; > @@ -204,8 +204,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, > unsigned long features) > { > ops->setup_mixer_out = dpu_hw_lm_setup_out; > - if (m->hwversion >= DPU_HW_VER_400) > - ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; > + if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features)) > + ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha; This will not work for all chipsets. In the catalog you have added BIT(DPU_MIXER_COMBINED_ALPHA) only for MIXER_SDM845_MASK but MIXER_SC7180_MASK is not updated. HW version of sc7180 is > DPU_HW_VER_400 so this would break both sc7180 and sc7280. Please update all the relevant chipset masks. > else > ops->setup_blend_config = dpu_hw_lm_setup_blend_config; > ops->setup_alpha_out = dpu_hw_lm_setup_color3;
On 6/2/2022 6:30 AM, Dmitry Baryshkov wrote: > Change dpu_mdss_cfg::perf to be a const pointer rather than embedding > the dpu_perf_cfg struct into the struct dpu_mdss_cfg. > > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 20 +++++++++---------- > .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 +++++----- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 16 +++++++-------- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++++++++--------- > 5 files changed, 33 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > index a7492dd6ed65..31767d0f7353 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > @@ -53,7 +53,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms, > crtc_plane_bw += pstate->plane_fetch_bw; > } > > - bw_factor = kms->catalog->perf.bw_inefficiency_factor; > + bw_factor = kms->catalog->perf->bw_inefficiency_factor; > if (bw_factor) { > crtc_plane_bw *= bw_factor; > do_div(crtc_plane_bw, 100); > @@ -90,7 +90,7 @@ static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms, > crtc_clk = max(pstate->plane_clk, crtc_clk); > } > > - clk_factor = kms->catalog->perf.clk_inefficiency_factor; > + clk_factor = kms->catalog->perf->clk_inefficiency_factor; > if (clk_factor) { > crtc_clk *= clk_factor; > do_div(crtc_clk, 100); > @@ -128,7 +128,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, > perf->core_clk_rate = kms->perf.fix_core_clk_rate; > } else { > perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc); > - perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib; > + perf->max_per_pipe_ib = kms->catalog->perf->min_dram_ib; > perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state); > } > > @@ -189,7 +189,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, > bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000); > DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw); > > - threshold = kms->catalog->perf.max_bw_high; > + threshold = kms->catalog->perf->max_bw_high; > > DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold); > > @@ -413,7 +413,7 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file, > const char __user *user_buf, size_t count, loff_t *ppos) > { > struct dpu_core_perf *perf = file->private_data; > - struct dpu_perf_cfg *cfg = &perf->catalog->perf; > + const struct dpu_perf_cfg *cfg = perf->catalog->perf; > u32 perf_mode = 0; > int ret; > > @@ -480,15 +480,15 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) > debugfs_create_u32("enable_bw_release", 0600, entry, > (u32 *)&perf->enable_bw_release); > debugfs_create_u32("threshold_low", 0600, entry, > - (u32 *)&catalog->perf.max_bw_low); > + (u32 *)&catalog->perf->max_bw_low); > debugfs_create_u32("threshold_high", 0600, entry, > - (u32 *)&catalog->perf.max_bw_high); > + (u32 *)&catalog->perf->max_bw_high); > debugfs_create_u32("min_core_ib", 0600, entry, > - (u32 *)&catalog->perf.min_core_ib); > + (u32 *)&catalog->perf->min_core_ib); > debugfs_create_u32("min_llcc_ib", 0600, entry, > - (u32 *)&catalog->perf.min_llcc_ib); > + (u32 *)&catalog->perf->min_llcc_ib); > debugfs_create_u32("min_dram_ib", 0600, entry, > - (u32 *)&catalog->perf.min_dram_ib); > + (u32 *)&catalog->perf->min_dram_ib); > debugfs_create_file("perf_mode", 0600, entry, > (u32 *)perf, &dpu_core_perf_mode_fops); > debugfs_create_u64("fix_core_clk_rate", 0600, entry, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > index 4829d1ce0cf8..1e4a4822fbf4 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > @@ -104,7 +104,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) > struct dpu_hw_wb *hw_wb; > struct dpu_hw_wb_qos_cfg qos_cfg; > struct dpu_mdss_cfg *catalog; > - struct dpu_qos_lut_tbl *qos_lut_tb; > + const struct dpu_qos_lut_tbl *qos_lut_tb; > > if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { > DPU_ERROR("invalid parameter(s)\n"); > @@ -118,11 +118,11 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) > memset(&qos_cfg, 0, sizeof(struct dpu_hw_wb_qos_cfg)); > qos_cfg.danger_safe_en = true; > qos_cfg.danger_lut = > - catalog->perf.danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; > + catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; > > - qos_cfg.safe_lut = catalog->perf.safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; > + qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; > > - qos_lut_tb = &catalog->perf.qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; > + qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; > qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0); > > if (hw_wb->ops.setup_qos_lut) > @@ -166,7 +166,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, > if (hw_wb->ops.setup_cdp) { > memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); > > - cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf.cdp_cfg > + cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg > [DPU_PERF_CDP_USAGE_NRT].wr_enable; > cdp_cfg.ubwc_meta_enable = > DPU_FORMAT_IS_UBWC(wb_cfg->dest.format); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 367279371e8d..a7040ca5da72 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -1750,7 +1750,7 @@ static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .vbif_count = ARRAY_SIZE(msm8998_vbif), > .vbif = msm8998_vbif, > .reg_dma_count = 0, > - .perf = msm8998_perf_data, > + .perf = &msm8998_perf_data, > .mdss_irqs = IRQ_SM8250_MASK, > }; > } > @@ -1781,7 +1781,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .vbif = sdm845_vbif, > .reg_dma_count = 1, > .dma_cfg = sdm845_regdma, > - .perf = sdm845_perf_data, > + .perf = &sdm845_perf_data, > .mdss_irqs = IRQ_SDM845_MASK, > }; > } > @@ -1812,7 +1812,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .vbif = sdm845_vbif, > .reg_dma_count = 1, > .dma_cfg = sdm845_regdma, > - .perf = sc7180_perf_data, > + .perf = &sc7180_perf_data, > .mdss_irqs = IRQ_SC7180_MASK, > }; > } > @@ -1845,7 +1845,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .vbif = sdm845_vbif, > .reg_dma_count = 1, > .dma_cfg = sm8150_regdma, > - .perf = sm8150_perf_data, > + .perf = &sm8150_perf_data, > .mdss_irqs = IRQ_SDM845_MASK, > }; > } > @@ -1876,7 +1876,7 @@ static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .vbif = sdm845_vbif, > .reg_dma_count = 1, > .dma_cfg = sm8150_regdma, > - .perf = sc8180x_perf_data, > + .perf = &sc8180x_perf_data, > .mdss_irqs = IRQ_SC8180X_MASK, > }; > } > @@ -1911,7 +1911,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .wb = sm8250_wb, > .reg_dma_count = 1, > .dma_cfg = sm8250_regdma, > - .perf = sm8250_perf_data, > + .perf = &sm8250_perf_data, > .mdss_irqs = IRQ_SM8250_MASK, > }; > } > @@ -1934,7 +1934,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .intf = sc7280_intf, > .vbif_count = ARRAY_SIZE(sdm845_vbif), > .vbif = sdm845_vbif, > - .perf = sc7280_perf_data, > + .perf = &sc7280_perf_data, > .mdss_irqs = IRQ_SC7280_MASK, > }; > } > @@ -1966,7 +1966,7 @@ static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg) > .vbif = sdm845_vbif, > .reg_dma_count = 1, > .dma_cfg = sdm845_regdma, > - .perf = qcm2290_perf_data, > + .perf = &qcm2290_perf_data, > .mdss_irqs = IRQ_SC7180_MASK, > }; > } > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 4225f58d8f97..64ed96b2fa3d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -868,7 +868,7 @@ struct dpu_mdss_cfg { > > /* Add additional block data structures here */ > > - struct dpu_perf_cfg perf; > + const struct dpu_perf_cfg *perf; > const struct dpu_format_extended *dma_formats; > const struct dpu_format_extended *cursor_formats; > const struct dpu_format_extended *vig_formats; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 9d2f0364d2c7..d8048b6862f9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -160,7 +160,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, > vbp = mode->vtotal - mode->vsync_end; > vpw = mode->vsync_end - mode->vsync_start; > vfp = mode->vsync_start - mode->vdisplay; > - hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; > + hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; > scale_factor = src_height > dst_height ? > mult_frac(src_height, 1, dst_height) : 1; > > @@ -309,7 +309,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, > } > > qos_lut = _dpu_hw_get_qos_lut( > - &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); > + &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); > > trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, > (fmt) ? fmt->base.pixel_format : 0, > @@ -336,9 +336,9 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, > u32 danger_lut, safe_lut; > > if (!pdpu->is_rt_pipe) { > - danger_lut = pdpu->catalog->perf.danger_lut_tbl > + danger_lut = pdpu->catalog->perf->danger_lut_tbl > [DPU_QOS_LUT_USAGE_NRT]; > - safe_lut = pdpu->catalog->perf.safe_lut_tbl > + safe_lut = pdpu->catalog->perf->safe_lut_tbl > [DPU_QOS_LUT_USAGE_NRT]; > } else { > fmt = dpu_get_dpu_format_ext( > @@ -346,14 +346,14 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, > fb->modifier); > > if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { > - danger_lut = pdpu->catalog->perf.danger_lut_tbl > + danger_lut = pdpu->catalog->perf->danger_lut_tbl > [DPU_QOS_LUT_USAGE_LINEAR]; > - safe_lut = pdpu->catalog->perf.safe_lut_tbl > + safe_lut = pdpu->catalog->perf->safe_lut_tbl > [DPU_QOS_LUT_USAGE_LINEAR]; > } else { > - danger_lut = pdpu->catalog->perf.danger_lut_tbl > + danger_lut = pdpu->catalog->perf->danger_lut_tbl > [DPU_QOS_LUT_USAGE_MACROTILE]; > - safe_lut = pdpu->catalog->perf.safe_lut_tbl > + safe_lut = pdpu->catalog->perf->safe_lut_tbl > [DPU_QOS_LUT_USAGE_MACROTILE]; > } > } > @@ -1225,7 +1225,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) > > memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); > > - cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg > + cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg > [DPU_PERF_CDP_USAGE_RT].rd_enable; > cdp_cfg.ubwc_meta_enable = > DPU_FORMAT_IS_UBWC(fmt);