| Message ID | 20220617122922.769562-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | clk: qcom: mmcc-msm8996: modernize the driver | expand |
On 17.06.2022 14:29, Dmitry Baryshkov wrote: > Move clock parent tables down, after the MMPLL declrataions, so that we > can use gpll hw clock fields in the next commit. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/clk/qcom/mmcc-msm8996.c | 364 ++++++++++++++++---------------- > 1 file changed, 182 insertions(+), 182 deletions(-) > > diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c > index bf0f8eb78989..27c92818c49c 100644 > --- a/drivers/clk/qcom/mmcc-msm8996.c > +++ b/drivers/clk/qcom/mmcc-msm8996.c > @@ -45,188 +45,6 @@ enum { > P_MMPLL4, > }; > > -static const struct parent_map mmss_xo_hdmi_map[] = { > - { P_XO, 0 }, > - { P_HDMIPLL, 1 } > -}; > - > -static const char * const mmss_xo_hdmi[] = { > - "xo", > - "hdmipll" > -}; > - > -static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { > - { P_XO, 0 }, > - { P_DSI0PLL, 1 }, > - { P_DSI1PLL, 2 } > -}; > - > -static const char * const mmss_xo_dsi0pll_dsi1pll[] = { > - "xo", > - "dsi0pll", > - "dsi1pll" > -}; > - > -static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_gpll0_gpll0_div[] = { > - "xo", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_dsibyte_map[] = { > - { P_XO, 0 }, > - { P_DSI0PLL_BYTE, 1 }, > - { P_DSI1PLL_BYTE, 2 } > -}; > - > -static const char * const mmss_xo_dsibyte[] = { > - "xo", > - "dsi0pllbyte", > - "dsi1pllbyte" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL1, 2 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "mmpll1", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL3, 3 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "mmpll3", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL5, 2 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "mmpll5", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL4, 3 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "mmpll4", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL9, 2 }, > - { P_MMPLL2, 3 }, > - { P_MMPLL8, 4 }, > - { P_GPLL0, 5 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { > - "xo", > - "mmpll0", > - "mmpll9", > - "mmpll2", > - "mmpll8", > - "gpll0" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL9, 2 }, > - { P_MMPLL2, 3 }, > - { P_MMPLL8, 4 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "mmpll9", > - "mmpll2", > - "mmpll8", > - "gpll0", > - "gpll0_div" > -}; > - > -static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { > - { P_XO, 0 }, > - { P_MMPLL0, 1 }, > - { P_MMPLL1, 2 }, > - { P_MMPLL4, 3 }, > - { P_MMPLL3, 4 }, > - { P_GPLL0, 5 }, > - { P_GPLL0_DIV, 6 } > -}; > - > -static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { > - "xo", > - "mmpll0", > - "mmpll1", > - "mmpll4", > - "mmpll3", > - "gpll0", > - "gpll0_div" > -}; > - > static struct clk_fixed_factor gpll0_div = { > .mult = 1, > .div = 2, > @@ -471,6 +289,188 @@ static struct clk_alpha_pll_postdiv mmpll9 = { > }, > }; > > +static const struct parent_map mmss_xo_hdmi_map[] = { > + { P_XO, 0 }, > + { P_HDMIPLL, 1 } > +}; > + > +static const char * const mmss_xo_hdmi[] = { > + "xo", > + "hdmipll" > +}; > + > +static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { > + { P_XO, 0 }, > + { P_DSI0PLL, 1 }, > + { P_DSI1PLL, 2 } > +}; > + > +static const char * const mmss_xo_dsi0pll_dsi1pll[] = { > + "xo", > + "dsi0pll", > + "dsi1pll" > +}; > + > +static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_gpll0_gpll0_div[] = { > + "xo", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_dsibyte_map[] = { > + { P_XO, 0 }, > + { P_DSI0PLL_BYTE, 1 }, > + { P_DSI1PLL_BYTE, 2 } > +}; > + > +static const char * const mmss_xo_dsibyte[] = { > + "xo", > + "dsi0pllbyte", > + "dsi1pllbyte" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL1, 2 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "mmpll1", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL3, 3 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "mmpll3", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL5, 2 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "mmpll5", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL4, 3 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "mmpll4", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL9, 2 }, > + { P_MMPLL2, 3 }, > + { P_MMPLL8, 4 }, > + { P_GPLL0, 5 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { > + "xo", > + "mmpll0", > + "mmpll9", > + "mmpll2", > + "mmpll8", > + "gpll0" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL9, 2 }, > + { P_MMPLL2, 3 }, > + { P_MMPLL8, 4 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "mmpll9", > + "mmpll2", > + "mmpll8", > + "gpll0", > + "gpll0_div" > +}; > + > +static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { > + { P_XO, 0 }, > + { P_MMPLL0, 1 }, > + { P_MMPLL1, 2 }, > + { P_MMPLL4, 3 }, > + { P_MMPLL3, 4 }, > + { P_GPLL0, 5 }, > + { P_GPLL0_DIV, 6 } > +}; > + > +static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { > + "xo", > + "mmpll0", > + "mmpll1", > + "mmpll4", > + "mmpll3", > + "gpll0", > + "gpll0_div" > +}; > + > static const struct freq_tbl ftbl_ahb_clk_src[] = { > F(19200000, P_XO, 1, 0, 0), > F(40000000, P_GPLL0_DIV, 7.5, 0, 0), >
On 17.06.2022 14:29, Dmitry Baryshkov wrote: > As we are converting this platform to use DT clock bindings, add clocks > and clock-names properties to the MMCC device tree node. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Sidenote: would RPM XO work here, or is it broken on 8996? Konrad > arch/arm64/boot/dts/qcom/msm8996.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index dffb87a5ee74..0c7b7cd9f23e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -751,6 +751,22 @@ mmcc: clock-controller@8c0000 { > #reset-cells = <1>; > #power-domain-cells = <1>; > reg = <0x008c0000 0x40000>; > + clocks = <&xo_board>, > + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, > + <&gcc GPLL0>, > + <&dsi0_phy 1>, > + <&dsi0_phy 0>, > + <0>, > + <0>, > + <0>; > + clock-names = "xo", > + "gcc_mmss_noc_cfg_ahb_clk", > + "gpll0", > + "dsi0pll", > + "dsi0pllbyte", > + "dsi1pll", > + "dsi1pllbyte", > + "hdmipll"; > assigned-clocks = <&mmcc MMPLL9_PLL>, > <&mmcc MMPLL1_PLL>, > <&mmcc MMPLL3_PLL>, >
On Fri, 17 Jun 2022 15:29:20 +0300, Dmitry Baryshkov wrote: > Move clock parent tables down, after the MMPLL declrataions, so that we > can use gpll hw clock fields in the next commit. > > Applied, thanks! [4/6] clk: qcom: mmcc-msm8996: move clock parent tables down commit: 208c564fe66e2f76abb29468d067223eb50b3005 Best regards,
On Fri, 17 Jun 2022 15:29:22 +0300, Dmitry Baryshkov wrote: > As we are converting this platform to use DT clock bindings, add clocks > and clock-names properties to the MMCC device tree node. > > Applied, thanks! [6/6] arm64: dts: qcom: msm8996: add clocks to the MMCC device node commit: 48aa636285ad76c7cc08d080e4c2a1fb955b9f11 Best regards,
Update mmcc-msm8996 driver and bindings to use DT-specified clocks rather than fetching the clocks from the global clocks list. Dmitry Baryshkov (6): dt-bindings: clock: qcom,mmcc: fix clocks/clock-names definitions dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8996 clk: qcom: mmcc-msm8996: use ARRAY_SIZE instead of specifying num_parents clk: qcom: mmcc-msm8996: move clock parent tables down clk: qcom: mmcc-msm8996: use parent_hws/_data instead of parent_names arm64: dts: qcom: msm8996: add clocks to the MMCC device node .../devicetree/bindings/clock/qcom,mmcc.yaml | 162 ++- arch/arm64/boot/dts/qcom/msm8996.dtsi | 16 + drivers/clk/qcom/mmcc-msm8996.c | 1052 ++++++++++------- 3 files changed, 808 insertions(+), 422 deletions(-)