From patchwork Thu Jan 19 14:04:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 644172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D63B9C00A5A for ; Thu, 19 Jan 2023 14:05:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231373AbjASOFN (ORCPT ); Thu, 19 Jan 2023 09:05:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231374AbjASOFJ (ORCPT ); Thu, 19 Jan 2023 09:05:09 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A082074E94 for ; Thu, 19 Jan 2023 06:05:07 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id e19-20020a05600c439300b003db1cac0c1fso2157358wmn.5 for ; Thu, 19 Jan 2023 06:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=9dXl5MSAf6THUl/3TA+I7jX3wEzwzpDXufOnVHww1WE=; b=uA2hhR0cBXUfloKo6JvvK7dyc314WNntf+GxNQLjpCdE5UB14EXGT8mjXjOLG84kTL zM7QyUYCAKrEqvpaVZy9KFXWuZXC1kewLqywsUGhwhMJlKGBTv1ZNmduXnlqXoz7nptY 8lAiVPZIWDt7Pm/224Fh7/Hc74Ebf35Umh5V5YG9PWYuGV1zqW6fhTPKqjyCyi7qfgCv LfXnw8JrH3gVi49TaA9XLgvk5cjESP1fm7XgD2DR6pUm5OmhAZ7gZyDryiFaiZ73SuhM jMI8wD8IzW8bBlDn2LyA0v/9c4vKhiMLPt+aPAlel5Z9SZKwKs1setpw8m97FRq+wnHQ NfJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9dXl5MSAf6THUl/3TA+I7jX3wEzwzpDXufOnVHww1WE=; b=5CewcYfW65YcaOtX+3loPNPWLhshnfhA6tmyoeHflMBiM5Uhy79bvHLpfsny2ZqxFX 660aWBTBXWNSCxK2v43PeXOcIlBS6OiowbfwV5ugeRjfQsOvK9ti+vedMqvHtBFCKeRd 8N3cR12zmApA8YPQgVnq4yCHdkPACFifDXB6o1q/Y2xKd9X1x+LaOeWdx+jjy5vSyIXu tQC8EAywwWz1VRAbEwp87gqOCUqDG0keDMkWF9d0LMXowDpumDXf/wFcCyZEueH1WFj7 NHy/4oizeSx7JqEZqzqUDlkSJsTEt10XarSDGf1O0ZXylI1ygDXZU0z9DI7JFj1uBplg NYgA== X-Gm-Message-State: AFqh2ko5oenORjxV9F1X1+f8kthPUgri8+Y+FSdHyI6ApPyZ91aOciSX cR2EXZVPNaUTOJPtAGvGsirgKQ== X-Google-Smtp-Source: AMrXdXuFCeG5Oi9K6Cs7CIYf3ikTo6UoLal3U73PVjlaOwcshPkD6BKNJtNiRr5vPMOxClhadO/IBA== X-Received: by 2002:a05:600c:1d29:b0:3d9:69fd:7707 with SMTP id l41-20020a05600c1d2900b003d969fd7707mr19004751wms.2.1674137106143; Thu, 19 Jan 2023 06:05:06 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m10-20020a05600c4f4a00b003d96efd09b7sm5263883wmq.19.2023.01.19.06.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 06:05:05 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 00/12] sm8550: Add PCIe HC and PHY support Date: Thu, 19 Jan 2023 16:04:41 +0200 Message-Id: <20230119140453.3942340-1-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In order to make sure the bindings are properly updated, I decided to send the whole PCIe support for SM8550 in a single patchset. Sorry in advance for the inconvenience. For changelogs please look at each patch individually. Abel Vesa (12): dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 phy: qcom-qmp: pcs: Add v6 register offsets phy: qcom-qmp: pcs: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6 register offsets phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add SM8550 PCIe support arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 11 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 29 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 207 +++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 4 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 367 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 16 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 + .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 ++ .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 6 + 13 files changed, 812 insertions(+), 5 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h