mbox series

[v1,0/8] Add cmb dataset support for TPDM

Message ID 20230329084744.5705-1-quic_jinlmao@quicinc.com
Headers show
Series Add cmb dataset support for TPDM | expand

Message

Mao Jinlong March 29, 2023, 8:47 a.m. UTC
Continuous multi-bit (CMB) is responsible for collection of CMB data sets.
It monitors a bus of related signals (eg, a counter value) and an associated valid signal.

This patch series adds support to config of CMB registers.
Element Creation:
  CMB_CR.mode : Continuous mode or Trace on Change mode(cmb_mode)

Pattern Match Output (usually to CTI):
  CMB_XPR : Trigger pattern register value(cmb_trig_patt_val)
  CMB_XPMR : Trigger pattern mask register value(cmb_trig_patt_mask)

Timestamp Request Based on Input Pattern Match:
  CMB_TPR : Timestamp pattern register value(cmb_patt_val)
  CMB_TPMR : Timestamp pattern mask register value(cmb_patt_mask)
  CMB_TIER.patt_tsenab : Timestamps are requested upon CMB interface pattern match via
                         setting this bit to 1(cmb_patt_ts)

Timestamp Request Based on Input (usually from CTI):
  CMB_TIER.xtrig_tsenab : Timestamps are requested upon CMB cross trigger interface
                          timestamp request via setting this bit to 1(cmb_trig_ts)

Mux Select Registers:
  CMB_MSR : Configure Mux select registers(cmb_msr)

Once this series patches are applied properly, the new tpdm nodes should be observed at the tpdm path.
e.g.
/sys/devices/platform/soc@0/10c29000.tpdm/tpdm1 # ls -l | grep cmb

-rw-r--r--    1 root     0             4096 Jan  1 00:00 cmb_mode
-rw-r--r--    1 root     0             4096 Jan  1 00:00 cmb_msr
-rw-r--r--    1 root     0             4096 Jan  1 00:00 cmb_patt_mask
-rw-r--r--    1 root     0             4096 Jan  1 00:00 cmb_patt_ts
-rw-r--r--    1 root     0             4096 Jan  1 00:22 cmb_patt_val
-rw-r--r--    1 root     0             4096 Jan  1 00:59 cmb_trig_patt_mask
-rw-r--r--    1 root     0             4096 Jan  1 00:57 cmb_trig_patt_val
-rw-r--r--    1 root     0             4096 Jan  1 00:00 cmb_trig_ts
-rw-r--r--    1 root     0             4096 Jan  1 00:58 cmb_ts_all

This patch series depends on:
[v3,0/11] Add support to configure TPDM DSB subunit
https://patchwork.kernel.org/project/linux-arm-kernel/cover/1679551448-19160-1-git-send-email-quic_taozha@quicinc.com/

Codelinaro link:
https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-cmb-v1

Mao Jinlong (8):
  coresight-tpdm: Add CMB dataset support
  coresight-tpdm: Add support to configure CMB collection mode
  coresight-tpdm: Add pattern registers support for CMB data set
  coresight-tpdm: Add timestamp control register support for the CMB
  coresight-tpdm: Add msr register support for CMB
  dt-bindings: arm: Add support for TPDM CMB MSR register
  coresight-tpda: Add support to configure CMB element size
  dt-bindings: arm: Add support for TPDM CMB element size

 .../testing/sysfs-bus-coresight-devices-tpdm  |  63 +++
 .../bindings/arm/qcom,coresight-tpdm.yaml     |  26 +
 drivers/hwtracing/coresight/coresight-tpda.c  |  33 +-
 drivers/hwtracing/coresight/coresight-tpda.h  |   4 +
 drivers/hwtracing/coresight/coresight-tpdm.c  | 447 +++++++++++++++++-
 drivers/hwtracing/coresight/coresight-tpdm.h  |  60 +++
 6 files changed, 626 insertions(+), 7 deletions(-)

Comments

Krzysztof Kozlowski March 30, 2023, 7:51 a.m. UTC | #1
On 29/03/2023 10:47, Mao Jinlong wrote:
> Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register)
> for TPDM. It specifies the number of CMB MSR registers supported by
> the TDPM.
> 
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Krzysztof Kozlowski March 30, 2023, 7:54 a.m. UTC | #2
On 29/03/2023 10:47, Mao Jinlong wrote:
> Add property "qcom,cmb-elem-size" to support CMB element for TPDM.
> The associated aggregator will read this size before it is enabled.
> CMB element size currently only supports 8-bit, 32-bit and 64-bit.
> 
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
>  .../bindings/arm/qcom,coresight-tpdm.yaml        | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
> index 283dfb39d46f..c5169de81e58 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
> @@ -53,6 +53,14 @@ properties:
>      minimum: 32
>      maximum: 64
>  
> +  qcom,cmb-element-size:

s/size/bits/
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/property-units.yaml

> +    description:
> +      Specifies the CMB (Continuous multi-bit) element size supported by
> +      the monitor. The associated aggregator will read this size before it
> +      is enabled. CMB element size currently supports 8-bit, 32-bit, 64-bit.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [8, 32, 64]
> +
>    qcom,dsb_msr_num:
>      description:
>        Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
> @@ -95,6 +103,12 @@ required:
>    - clocks
>    - clock-names
>  
> +anyOf:
> +  - required:
> +      - qcom,dsb_msr_num

There is no such property.

> +  - required:
> +      - qcom,cmb-msr-num

Why this is part of this patch?

> +
>  additionalProperties: false
>  
>  examples:
> @@ -105,6 +119,8 @@ examples:
>        reg = <0x0684c000 0x1000>;
>  
>        qcom,dsb-element-size = <32>;
> +      qcom,cmb-element-size = <32>;
> +
>        qcom,dsb_msr_num = <16>;
>        qcom,cmb-msr-num = <6>;
>  

Best regards,
Krzysztof