From patchwork Fri May 19 14:31:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 684019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 145C4C77B7F for ; Fri, 19 May 2023 14:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232035AbjESOb3 (ORCPT ); Fri, 19 May 2023 10:31:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231959AbjESOb2 (ORCPT ); Fri, 19 May 2023 10:31:28 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F4B6E1 for ; Fri, 19 May 2023 07:31:27 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-24e3b69bc99so2606635a91.2 for ; Fri, 19 May 2023 07:31:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684506687; x=1687098687; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2i+4jZMYyJOuLHa5p2LrqOp9rYboDhqgn1MB/sFP3Yk=; b=NGH3s5VWcjCYJ467VCymIG56S/3e59VN9TouKrORlz1kUH9pDmPg+OhKrB7IREV6Rp kyfAqSlCnfHExdp468iMVrISs6R+GMlbQ1CNIlcI1H05fV8MvYoZ8rVO2Mb4OV5wKw3v I2bZ7wlj/bmDqIN8+0fwdCIE2/PYo+5mu5RzVhFiJ2YiTMpKd4F2lH6Vtg6aFyRA4ILl rv7jDg/JBqRVP9kP83q9iGSkkC1pc5qJ8m3npI278unfvFayw6rzteHKvQ45jeEz1yel WiqQADrAXSBPKyRx3xMRGcyYlXSv51Ab5b6XCaKL0GFBrwacjOCTB2sJDic4lu1vexJt qkWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684506687; x=1687098687; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2i+4jZMYyJOuLHa5p2LrqOp9rYboDhqgn1MB/sFP3Yk=; b=Eflb9pLcqci7XUKlW2UHhZm1gf7Z9NLjE4NwfEOV64V9nv4vVsVxF80Xe9onYdMVZ8 O3/gdx54KqZpiKurL1Vw64qtMEqgmBdqKKtCvkhjm+k4oFVlb6w2KpEWW0bRz5igSARD F8wSCleGPcorfMIxRGSmWP7UHQQzMuuBRmVQeWCmxe/VgjIRxysH8i4KnDeIqwEjvnSa pWmbX5B6pwUEbfOfl4V8DT6/pNi1tUujUlRPMSSmAcBuCrKWWaufemfJ8Kox/Qu6IXMF Nif9QZJ+rO0cBc5m3L6FGkFZBsj3XWHzgEcOUZ1k55WJ7OLryoGK2UjUK7eInSfMzWnL DIsQ== X-Gm-Message-State: AC+VfDwmm0Vx/UyaQaueY+m6M8OmiRLFmM39zmFbot5+7IVmhpx3Y6l6 nSYU5Pi7iW9mQ0uNgVtA+vJr X-Google-Smtp-Source: ACHHUZ4YSPrAcDxn1zJ2i51SAYCP+PWm804ct+HEEvUvMD4g7cLt1qC2faNpG6gOsV6P1sjOQukimg== X-Received: by 2002:a17:90a:c712:b0:250:2192:1bff with SMTP id o18-20020a17090ac71200b0025021921bffmr2556538pjt.23.1684506686731; Fri, 19 May 2023 07:31:26 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.13]) by smtp.gmail.com with ESMTPSA id 30-20020a17090a09a100b00250d908a771sm1634845pjo.50.2023.05.19.07.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 07:31:26 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 0/8] PCI: qcom: Do not advertise hotplug capability Date: Fri, 19 May 2023 20:01:09 +0530 Message-Id: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, The SoCs making use of Qualcomm PCIe controllers do not support the PCIe hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, this series clears the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence for all IP versions to not advertise the hotplug capability for the controller. Testing ======= This series has been tested on DB845c (SDM845 SoC) and Lenovo Thinkpad X13s (SC8280XP SoC). Thanks, Mani Changes in v2: * Collected tags * Moved the HPC clearing to a separate function and reused across different configs Manivannan Sadhasivam (8): PCI: qcom: Use DWC helpers for modifying the read-only DBI registers PCI: qcom: Disable write access to read only registers for IP v2.9.0 PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0 PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 PCI: qcom: Do not advertise hotplug capability for IP v1.0.0 PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 drivers/pci/controller/dwc/pcie-qcom.c | 73 ++++++++++++++------------ 1 file changed, 38 insertions(+), 35 deletions(-)