| Message ID | 20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org |
|---|---|
| Headers | show |
| Series | Update parts of PLL_TEST_CTL(_U) if required | expand |
On Thu, 01 Jun 2023 11:39:06 +0200, Konrad Dybcio wrote: > Some recent-ish clock drivers touching on the "standard" Alpha PLLs > have been specifying the values that should be written into the CTL > registers as mask-value combos, but that wasn't always reflected > properly (or at all). This series tries to fix that without affecitng > the drivers that actually provide the full register values. > > > [...] Applied, thanks! [1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) commit: 501624339466a7896bb8a1f048cf8dcfd54b174e [2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties commit: e88c533d8a2a0fe84bb54cff1569bd079ad3512c Best regards,
Some recent-ish clock drivers touching on the "standard" Alpha PLLs have been specifying the values that should be written into the CTL registers as mask-value combos, but that wasn't always reflected properly (or at all). This series tries to fix that without affecitng the drivers that actually provide the full register values. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Konrad Dybcio (2): clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) clk: qcom: gcc-sm6115: Add missing PLL config properties drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++---- drivers/clk/qcom/clk-alpha-pll.h | 2 ++ drivers/clk/qcom/gcc-sm6115.c | 8 ++++++++ 3 files changed, 25 insertions(+), 4 deletions(-) --- base-commit: 571d71e886a5edc89b4ea6d0fe6f445282938320 change-id: 20230601-topic-alpha_ctl-ab0dc0ad3654 Best regards,