mbox series

[0/4] phy: qcom-qmp-combo: correct sm8550 PHY programming

Message ID 20230906075823.7957-1-dmitry.baryshkov@linaro.org
Headers show
Series phy: qcom-qmp-combo: correct sm8550 PHY programming | expand

Message

Dmitry Baryshkov Sept. 6, 2023, 7:58 a.m. UTC 
Fix one bug and several small issues with the QMP USB+DP PHY programming
on the Qualcomm SM8550 platform.

Dmitry Baryshkov (4):
  phy: qcom-qmp-combo: correct sm8550 PHY programming
  phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registers
  phy: qcom-qmp-usb: move PCS v6 register to the proper header
  phy: qcom-qmp-combo: use v6 registers in v6 regs layout

 drivers/phy/qualcomm/phy-qcom-qmp-combo.c     | 50 +++++++++----------
 .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h    | 27 +++-------
 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h    | 19 ++++++-
 3 files changed, 49 insertions(+), 47 deletions(-)

Comments

Neil Armstrong Sept. 6, 2023, 8:01 a.m. UTC | #1 
On 06/09/2023 09:58, Dmitry Baryshkov wrote:
> Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout.

Why that if the registers are the same as v5 ?

Neil

> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c      | 12 ++++++------
>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h |  2 ++
>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h     |  4 ++++
>   3 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index bff6231d7de3..9c71a132afea 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -194,14 +194,14 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
>   };
>   
>   static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> -	[QPHY_SW_RESET]			= QPHY_V5_PCS_SW_RESET,
> -	[QPHY_START_CTRL]		= QPHY_V5_PCS_START_CONTROL,
> -	[QPHY_PCS_STATUS]		= QPHY_V5_PCS_PCS_STATUS1,
> -	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_POWER_DOWN_CONTROL,
> +	[QPHY_SW_RESET]			= QPHY_V6_PCS_SW_RESET,
> +	[QPHY_START_CTRL]		= QPHY_V6_PCS_START_CONTROL,
> +	[QPHY_PCS_STATUS]		= QPHY_V6_PCS_PCS_STATUS1,
> +	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_POWER_DOWN_CONTROL,
>   
>   	/* In PCS_USB */
> -	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
> -	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> +	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
> +	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
>   
>   	[QPHY_COM_RESETSM_CNTRL]	= QSERDES_V6_COM_RESETSM_CNTRL,
>   	[QPHY_COM_C_READY_STATUS]	= QSERDES_V6_COM_C_READY_STATUS,
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> index 7c16af0b1cc3..0d0089898240 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> @@ -8,6 +8,8 @@
>   
>   /* Only for QMP V6 PHY - USB3 have different offsets than V5 */
>   #define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1		0x00
> +#define QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL		0x08
> +#define QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR		0x14
>   #define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x18
>   #define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x3c
>   #define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
> index c95d3fabd108..496c36522e55 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
> @@ -7,6 +7,10 @@
>   #define QCOM_PHY_QMP_PCS_V6_H_
>   
>   /* Only for QMP V6 PHY - USB/PCIe PCS registers */
> +#define QPHY_V6_PCS_SW_RESET			0x000
> +#define QPHY_V6_PCS_PCS_STATUS1			0x014
> +#define QPHY_V6_PCS_POWER_DOWN_CONTROL		0x040
> +#define QPHY_V6_PCS_START_CONTROL		0x044
>   #define QPHY_V6_PCS_LOCK_DETECT_CONFIG1		0x0c4
>   #define QPHY_V6_PCS_LOCK_DETECT_CONFIG2		0x0c8
>   #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3		0x0cc
Neil Armstrong Sept. 6, 2023, 8:02 a.m. UTC | #2 
On 06/09/2023 09:58, Dmitry Baryshkov wrote:
> Move PCS_USB3_POWER_STATE_CONFIG1 register programming from pcs_tbl to
> the pcs_usb_tbl, where it belongs. Also, while we are at it, correct the
> offset of this register to point to 0x00, as expected.

Konrad already sent this https://lore.kernel.org/all/20230829-topic-8550_usbphy-v1-1-599ddbfa094a@linaro.org/

> 
> Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550")
> Fixes: 39bbf82d8c2b ("phy: qcom-qmp: pcs-usb: Add v6 register offsets")
> Cc: Abel Vesa <abel.vesa@linaro.org>
> Cc: stable@vger.kernel.org
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c      | 2 +-
>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h | 2 +-
>   2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index cbb28afce135..41b9be56eead 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -859,7 +859,6 @@ static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
>   	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
>   	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
> -	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
>   };
>   
>   static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
> @@ -867,6 +866,7 @@ static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
>   	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
>   	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
> +	QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
>   };
>   
>   static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> index 9510e63ba9d8..5409ddcd3eb5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> @@ -12,7 +12,6 @@
>   #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3		0xcc
>   #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6		0xd8
>   #define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1		0xdc
> -#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1	0x90
>   #define QPHY_USB_V6_PCS_RX_SIGDET_LVL			0x188
>   #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L		0x190
>   #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H		0x194
> @@ -23,6 +22,7 @@
>   #define QPHY_USB_V6_PCS_EQ_CONFIG1			0x1dc
>   #define QPHY_USB_V6_PCS_EQ_CONFIG5			0x1ec
>   
> +#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1	0x00
>   #define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x18
>   #define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x3c
>   #define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40
Dmitry Baryshkov Sept. 6, 2023, 8:25 a.m. UTC | #3 
On Wed, 6 Sept 2023 at 11:01, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 06/09/2023 09:58, Dmitry Baryshkov wrote:
> > Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout.
>
> Why that if the registers are the same as v5 ?

Because otherwise it is too easy to use the incorrect register when
adding a new register to the regs layout. Been there.

>
> Neil
>
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >   drivers/phy/qualcomm/phy-qcom-qmp-combo.c      | 12 ++++++------
> >   drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h |  2 ++
> >   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h     |  4 ++++
> >   3 files changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > index bff6231d7de3..9c71a132afea 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > @@ -194,14 +194,14 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> >   };
> >
> >   static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> > -     [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
> > -     [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
> > -     [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
> > -     [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
> > +     [QPHY_SW_RESET]                 = QPHY_V6_PCS_SW_RESET,
> > +     [QPHY_START_CTRL]               = QPHY_V6_PCS_START_CONTROL,
> > +     [QPHY_PCS_STATUS]               = QPHY_V6_PCS_PCS_STATUS1,
> > +     [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_POWER_DOWN_CONTROL,
> >
> >       /* In PCS_USB */
> > -     [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
> > -     [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> > +     [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
> > +     [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> >
> >       [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V6_COM_RESETSM_CNTRL,
> >       [QPHY_COM_C_READY_STATUS]       = QSERDES_V6_COM_C_READY_STATUS,
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> > index 7c16af0b1cc3..0d0089898240 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
> > @@ -8,6 +8,8 @@
> >
> >   /* Only for QMP V6 PHY - USB3 have different offsets than V5 */
> >   #define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1                0x00
> > +#define QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL                0x08
> > +#define QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR               0x14
> >   #define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL    0x18
> >   #define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2   0x3c
> >   #define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L         0x40
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
> > index c95d3fabd108..496c36522e55 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
> > @@ -7,6 +7,10 @@
> >   #define QCOM_PHY_QMP_PCS_V6_H_
> >
> >   /* Only for QMP V6 PHY - USB/PCIe PCS registers */
> > +#define QPHY_V6_PCS_SW_RESET                 0x000
> > +#define QPHY_V6_PCS_PCS_STATUS1                      0x014
> > +#define QPHY_V6_PCS_POWER_DOWN_CONTROL               0x040
> > +#define QPHY_V6_PCS_START_CONTROL            0x044
> >   #define QPHY_V6_PCS_LOCK_DETECT_CONFIG1             0x0c4
> >   #define QPHY_V6_PCS_LOCK_DETECT_CONFIG2             0x0c8
> >   #define QPHY_V6_PCS_LOCK_DETECT_CONFIG3             0x0cc
>