| Message ID | 20240221-spmi-multi-master-support-v5-0-3255ca413a0b@linaro.org |
|---|---|
| Headers | show |
| Series | spmi: pmic-arb: Add support for multiple buses | expand |
On 21/02/2024 13:52, Abel Vesa wrote: > Add dedicated schema for PMIC ARB v7 as it allows multiple > buses by declaring them as child nodes. These child nodes > will follow the generic spmi bus bindings. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > + > +description: | > + The SPMI PMIC Arbiter v7 is found on Snapdragon chipsets. It is an SPMI > + controller with wrapping arbitration logic to allow for multiple on-chip > + devices to control up to 2 SPMI separate buses. > + > + The PMIC Arbiter can also act as an interrupt controller, providing interrupts > + to slave devices. > + > +properties: > + compatible: > + const: qcom,spmi-pmic-arb-v7 I dislike the versioning. Previous PMIC ARB binding said "it will cover everything" and now it turns out that everything is not everything. I would suggest SoC specific compatibles. > + > + reg: > + items: > + - description: core registers > + - description: tx-channel per virtual slave regosters > + - description: rx-channel (called observer) per virtual slave registers > + > + reg-names: > + items: > + - const: core > + - const: chnls > + - const: obsrvr > + > + ranges: true > + > + '#address-cells': > + const: 2 > + > + '#size-cells': > + const: 2 > + > + qcom,ee: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 5 > + description: > > + indicates the active Execution Environment identifier > + > + qcom,channel: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 5 > + description: > > + which of the PMIC Arb provided channels to use for accesses We should probably deprecate qcom,bus-id in qcom,spmi-pmic-arb.yaml. > + > +patternProperties: > + "spmi@[0-1]$": > + type: object > + $ref: /schemas/spmi/spmi.yaml On this level: unevaluatedProperties: false > + > +required: > + - compatible > + - reg-names > + - qcom,ee > + - qcom,channel > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + spmi: arbiter@c400000 { > + compatible = "qcom,spmi-pmic-arb-v7"; > + reg = <0x0c400000 0x3000>, > + <0x0c500000 0x4000000>, > + <0x0c440000 0x80000>; > + reg-names = "core", "chnls", "obsrvr"; > + > + qcom,ee = <0>; > + qcom,channel = <0>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + spmi_bus0: spmi@0 { > + reg = <0 0x0c42d000 0 0x4000>, > + <0 0x0c4c0000 0 0x10000>; > + reg-names = "cnfg", "intr"; > + > + interrupt-names = "periph_irq"; > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <4>; > + > + qcom,bus-id = <0>; Please drop. Same in second instance. Best regards, Krzysztof
This RFC prepares for and adds support for 2 buses, which is supported in HW starting with version 7. Until now, none of the currently supported platforms in upstream have used the second bus. The X1E80100 platform, on the other hand, needs the second bus for the USB2.0 to work as there are 3 SMB2360 PMICs which provide eUSB2 repeaters and they are all found on the second bus. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Changes in v5: - Dropped the RFC as there aren't any concerns about the approach anymore - Dropped the unused dev and res variables from pmic_arb_get_obsrvr_chnls_v2 - Link to v4: https://lore.kernel.org/r/20240220-spmi-multi-master-support-v4-0-dc813c878ba8@linaro.org Changes in v4: - Fixed comment above pmic_arb_init_apid_v7 by dropping the extra "bus" word - Swicthed to devm_platform_ioremap_resource_byname for obsrvr and chnls. The core remains with platform_get_resource_byname as we need the core size. - Dropped comment from probe related to the need of platform_get_resource_byname as it not true anymore. - Dropped the qcom,bus-id optional property. - Link to v3: https://lore.kernel.org/r/20240214-spmi-multi-master-support-v3-0-0bae0ef04faf@linaro.org Changes in v3: - Split the change into 3 separate patches. First 2 patches are moving apid init and core resources into version specific ops. Third one is adding the support for 2 buses and dedicated compatible. - Added separate bindings patch - Link to v2: https://lore.kernel.org/r/20240213-spmi-multi-master-support-v2-1-b3b102326906@linaro.org Changes in v2: - Reworked it so that it registers a spmi controller for each bus rather than relying on the generic framework to pass on the bus (master) id. - Link to v1: https://lore.kernel.org/r/20240207-spmi-multi-master-support-v1-0-ce57f301c7fd@linaro.org --- Abel Vesa (4): dt-bindings: spmi: Add PMIC ARB v7 schema spmi: pmic-arb: Make the APID init a version operation spmi: pmic-arb: Make core resources acquiring a version operation spmi: pmic-arb: Add multi bus support .../bindings/spmi/qcom,spmi-pmic-arb-v7.yaml | 119 +++ drivers/spmi/spmi-pmic-arb.c | 949 +++++++++++++-------- 2 files changed, 698 insertions(+), 370 deletions(-) --- base-commit: 4893c639cc3659cefaa675bf1e59f4e7571afb5c change-id: 20240207-spmi-multi-master-support-832a704b779b Best regards,