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Fri, 14 Jun 2024 03:18:26 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ec05bf44c4sm5000241fa.9.2024.06.14.03.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 03:18:25 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH v3 0/5] phy: qcom: qmp-pcie: drop second clock-output-names entry Date: Fri, 14 Jun 2024 13:18:23 +0300 Message-Id: <20240614-fix-pcie-phy-compat-v3-0-730d1811acf4@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAO8YbGYC/33NzQqDMAzA8VeRnpfRL0V32nuMHVqNGthsaaVMx Hdf9TIGY8d/SH5ZWcRAGNmlWFnARJHclEOdCtaOZhoQqMvNJJeal1JATy/wLSH4cYHWPb2ZwfK +02h1ZTvD8qUPmNcO9XbPPVKcXViOJ0ns0/9eEsChNkaL0jZS8fr6oMkEd3ZhYDuY5AephP6Ny Iw0Da8rhaZUtv9Ctm17A/nORbv8AAAA To: Vinod Koul , Kishon Vijay Abraham I , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2468; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=e/vS57MZRDtlro2SWvpS0gu0uEi42A6fSDn9ZPw9edg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmbBjwQrd5js8BXipsqsF5cpu5SbQHYqeKPfwwD JdYmlmoThyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZmwY8AAKCRCLPIo+Aiko 1agVB/9WS3uiu3HZIel16w7kPNn4LdNLQX7XqhyLY9sHu6oe1PD1PpxqXReCWlgn3W3g9Kcxtpz H9+ur40bZ2unxnckJ1e3Go1juItrgf9O4RrIgGblqqeaxdBfTcwSItG8XQaYothSKlb9IcYNiKA e5wCnDgFfa+pqqsLs8GCiJkjM87kb6KQPh0JHRaTUiS4ZcAvPvMO8sITHlRqU+hNkQynETq/uiP SGot13W3gfp9bU95srZco4aCiYPufBAGNKktkk928d1nNVLbdv5HRdboy+oIM2sAxhfk/uwufAI sOClMbo24MaYPpyVH8ifUcs7lBJ5lHN/uHrGz0zic1Ps1r52 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A While testing the linux-next on SM8450-HDK I noticed that one of the PCIe hosts stays in the deferred state, because the corresponding PHY isn't probed. A quick debug pointed out that while the patches that added support for the PIPE AUX clock to the PHY driver have landed, corresponding DT changes were not picked up for 6.10. Restore the compatibility with the existing DT files by dropping the second entry in the clock-output-names array and always generating the corresponding name on the fly. To: Vinod Koul To: Kishon Vijay Abraham I To: Neil Armstrong To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Bjorn Andersson To: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Cc: devicetree@vger.kernel.org Signed-off-by: Dmitry Baryshkov Changes in v3: - Also added DT bits to remove DT warning - Link to v2: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v2-0-990863ea53bf@linaro.org Changes in v2: - Fixed generated AUX clock name (Neil) - Link to v1: https://lore.kernel.org/r/20240521-fix-pcie-phy-compat-v1-0-8aa415b92308@linaro.org --- Dmitry Baryshkov (5): phy: qcom: qmp-pcie: restore compatibility with existing DTs dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock name arm64: dts: qcom: sm8450: drop second clock name from clock-output-names arm64: dts: qcom: sm8550: drop second clock name from clock-output-names arm64: dts: qcom: sm8650: drop second clock name from clock-output-names .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +------ arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------ 5 files changed, 7 insertions(+), 15 deletions(-) --- base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0 change-id: 20240521-fix-pcie-phy-compat-b0fd4eb46bda Best regards,