| Message ID | 20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org |
|---|---|
| Headers | show |
| Series | PCI: qcom: Simulate PCIe hotplug using 'global' interrupt | expand |
On 17.07.2024 7:03 PM, Manivannan Sadhasivam via B4 Relay wrote: > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Currently, the IRQ device name for both of these IRQs doesn't have Qcom > specific prefix and PCIe domain number. This causes 2 issues: > > 1. Pollutes the global IRQ namespace since 'global' is a common name. > 2. When more than one EP controller instance is present in the SoC, naming > conflict will occur. > > Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ > names to uniquely identify the IRQs and also to fix the above mentioned > issues. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- lgtm Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On Wed, 17 Jul 2024 22:33:08 +0530, Manivannan Sadhasivam wrote: > Kishon's TI email ID is not active anymore, so use his korg ID. Also, since > I've been maintaining the PCI endpoint framework, I'm willing to maintain > the DT binding as well. So add myself as the Co-maintainer. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > Documentation/devicetree/bindings/pci/pci-ep.yaml | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
On Wed, Jul 17, 2024 at 10:33:16PM +0530, Manivannan Sadhasivam wrote: > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > to the host CPU. This interrupt can be used by the device driver to > identify events such as PCIe link specific events, safety events, etc... > > Hence, document it in the binding along with the existing MSI interrupts. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > index d8c0afaa4b19..0d68ce073383 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > @@ -55,11 +55,12 @@ properties: > - const: aggre1 # Aggre NoC PCIe1 AXI clock > > interrupts: > - minItems: 8 > - maxItems: 8 > + minItems: 9 ABI break > + maxItems: 9 > > interrupt-names: > items: > + - const: global ABI break. You can't add a new entry at the beginning of the list. > - const: msi0 > - const: msi1 > - const: msi2 > @@ -142,7 +143,8 @@ examples: > "aggre0", > "aggre1"; > > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > @@ -150,7 +152,7 @@ examples: > <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "msi0", "msi1", "msi2", "msi3", > + interrupt-names = "global", "msi0", "msi1", "msi2", "msi3", > "msi4", "msi5", "msi6", "msi7"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > > -- > 2.25.1 >
Hi, This series adds support to simulate PCIe hotplug using the Qcom specific 'global' IRQ. Historically, Qcom PCIe RC controllers lack standard hotplug support. So when an endpoint is attached to the SoC, users have to rescan the bus manually to enumerate the device. But this can be avoided by simulating the PCIe hotplug using Qcom specific way. Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt to the host CPUs. The device driver can use this event to identify events such as PCIe link specific events, safety events etc... One such event is the PCIe Link up event generated when an endpoint is detected on the bus and the Link is 'up'. This event can be used to simulate the PCIe hotplug in the Qcom SoCs. So add support for capturing the PCIe Link up event using the 'global' interrupt in the driver. Once the Link up event is received, the bus underneath the host bridge is scanned to enumerate PCIe endpoint devices, thus simulating hotplug. This series also has some cleanups to the Qcom PCIe EP controller driver for interrupt handling. Testing ======= This series is tested on Qcom SM8450 based development board that has 2 SoCs connected over PCIe. - Mani Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Changes in v2: - Added CONFIG_PCI_DOMAINS_GENERIC guard for domain_nr - Switched to dev_WARN_ONCE() for unhandled interrupts - Squashed the 'linux,pci-domain' bindings patches into one - Link to v1: https://lore.kernel.org/r/20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org --- Manivannan Sadhasivam (13): PCI: qcom-ep: Drop the redundant masking of global IRQ events PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event dt-bindings: PCI: pci-ep: Update Maintainers dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property PCI: endpoint: Assign PCI domain number for endpoint controllers PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes dt-bindings: PCI: qcom: Add 'global' interrupt dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt PCI: qcom: Simulate PCIe hotplug using 'global' interrupt arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node Documentation/devicetree/bindings/pci/pci-ep.yaml | 14 +++++- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 4 +- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++-- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 +++-- drivers/pci/controller/dwc/pcie-qcom-ep.c | 21 +++++++-- drivers/pci/controller/dwc/pcie-qcom.c | 55 +++++++++++++++++++++- drivers/pci/endpoint/pci-epc-core.c | 10 ++++ include/linux/pci-epc.h | 2 + 12 files changed, 116 insertions(+), 17 deletions(-) --- base-commit: 91e3b24eb7d297d9d99030800ed96944b8652eaf change-id: 20240715-pci-qcom-hotplug-bcde1c13d91f Best regards,