Message ID | 20240822-qcs8300-gcc-v2-0-b310dfa70ad8@quicinc.com |
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Thu, 22 Aug 2024 11:27:34 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47MBRYOL010209 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Aug 2024 11:27:34 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 22 Aug 2024 04:27:29 -0700 From: Imran Shaik <quic_imrashai@quicinc.com> Subject: [PATCH v2 0/2] clk: qcom: Add support for GCC on QCS8300 Date: Thu, 22 Aug 2024 16:57:17 +0530 Message-ID: <20240822-qcs8300-gcc-v2-0-b310dfa70ad8@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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clk: qcom: Add support for GCC on QCS8300
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This series adds the dt-bindings and driver support for GCC on QCS8300 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> --- Changes in v2: - Removed the QCS8300 SoC info series dependency in cover letter as per the review comments from Krzysztof. - Link to v1: https://lore.kernel.org/r/20240820-qcs8300-gcc-v1-0-d81720517a82@quicinc.com --- Imran Shaik (2): dt-bindings: clock: qcom: Add GCC clocks for QCS8300 clk: qcom: Add support for Global Clock Controller on QCS8300 .../bindings/clock/qcom,qcs8300-gcc.yaml | 66 + drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-qcs8300.c | 3640 ++++++++++++++++++++ include/dt-bindings/clock/qcom,qcs8300-gcc.h | 234 ++ 5 files changed, 3951 insertions(+) --- base-commit: bb1b0acdcd66e0d8eedee3570d249e076b89ab32 change-id: 20240820-qcs8300-gcc-433023269b36 Best regards,