| Message ID | 20240823-x1e80100-phy-add-gen4x4-v3-0-b7765631ca01@linaro.org |
|---|---|
| Headers | show |
| Series | phy: qcom: qmp-pcie: Add support for Gen4 4-lane mode for X1E80100 | expand |
On Fri, 23 Aug 2024 10:04:14 +0300, Abel Vesa wrote: > On all X Elite boards currently supported upstream, the NVMe sits > on the PCIe 6. Until now that has been configured in dual lane mode > only. The schematics reveal that the NVMe is actually using 4 lanes. > So add support for the 4-lane mode and document the compatible for it. > > This patchset depends on: > https://lore.kernel.org/all/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.org/ > > [...] Applied, thanks! [1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4 commit: 0c5f4d23f77631f657b60ef660676303f7620688 [2/2] phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 commit: 9dab00ee95447b286ebb0ada3a5edc00beab3750 Best regards,
On 29/08/2024 21:05, Vinod Koul wrote: > > On Fri, 23 Aug 2024 10:04:14 +0300, Abel Vesa wrote: >> On all X Elite boards currently supported upstream, the NVMe sits >> on the PCIe 6. Until now that has been configured in dual lane mode >> only. The schematics reveal that the NVMe is actually using 4 lanes. >> So add support for the 4-lane mode and document the compatible for it. >> >> This patchset depends on: >> https://lore.kernel.org/all/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.org/ >> >> [...] > > Applied, thanks! > > [1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4 > commit: 0c5f4d23f77631f657b60ef660676303f7620688 Heh, we discussed yesterday on IRC that this should wait. Why do we keep discussing things in private... Best regards, Krzysztof
On 30-08-24, 12:01, Krzysztof Kozlowski wrote: > On 29/08/2024 21:05, Vinod Koul wrote: > > > > On Fri, 23 Aug 2024 10:04:14 +0300, Abel Vesa wrote: > >> On all X Elite boards currently supported upstream, the NVMe sits > >> on the PCIe 6. Until now that has been configured in dual lane mode > >> only. The schematics reveal that the NVMe is actually using 4 lanes. > >> So add support for the 4-lane mode and document the compatible for it. > >> > >> This patchset depends on: > >> https://lore.kernel.org/all/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.org/ > >> > >> [...] > > > > Applied, thanks! > > > > [1/2] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4 > > commit: 0c5f4d23f77631f657b60ef660676303f7620688 > > Heh, we discussed yesterday on IRC that this should wait. I must have miseed that... > Why do we keep discussing things in private... This ideally should have followed up as a reply to this thread...
On all X Elite boards currently supported upstream, the NVMe sits on the PCIe 6. Until now that has been configured in dual lane mode only. The schematics reveal that the NVMe is actually using 4 lanes. So add support for the 4-lane mode and document the compatible for it. This patchset depends on: https://lore.kernel.org/all/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.org/ Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Changes in v3: - Moved the x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl right after proper serdes table, like Johan suggested - Picked Johan's R-b tags - Link to v2: https://lore.kernel.org/r/20240821-x1e80100-phy-add-gen4x4-v2-0-c34db42230e9@linaro.org Changes in v2: - Re-worded the commit message following Johan's suggestions. - Picked up Krzysztof's R-b tag for the bindings patch - Link to v1: https://lore.kernel.org/r/20240531-x1e80100-phy-add-gen4x4-v1-0-5c841dae7850@linaro.org --- Abel Vesa (2): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4 phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 ++++++++++++++++++++++ 2 files changed, 45 insertions(+) --- base-commit: 81528d2de965dafd6911a0f9a975fc30b25e7080 change-id: 20240531-x1e80100-phy-add-gen4x4-fa830a5505b6 Best regards,