| Message ID | 20240829082830.56959-1-quic_varada@quicinc.com |
|---|---|
| Headers | show |
| Series | Add NSS clock controller support for Qualcomm IPQ5332 | expand |
On Thu, Aug 29, 2024 at 01:58:25PM +0530, Varadarajan Narayanan wrote: > From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > > Add NSSCC clock and reset definitions for Qualcomm IPQ5332. > Enable interconnect provider ability for use by the ethernet > driver. > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v5: Marked #power-domain-cells as false > Included #interconnect-cells Then this might not be GCC-like clock controller or gcc.yaml should not include power-domain-cells. Best regards, Krzysztof
On Thu, Aug 29, 2024 at 01:58:26PM +0530, Varadarajan Narayanan wrote: > Update the GCC master/slave list to include couple of > more interfaces needed by the Network Subsystem Clock > Controller (NSSCC) > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > include/dt-bindings/interconnect/qcom,ipq5332.h | 4 ++++ > 1 file changed, 4 insertions(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Sat, 31 Aug 2024 at 09:11, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Thu, Aug 29, 2024 at 01:58:25PM +0530, Varadarajan Narayanan wrote: > > From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > > > > Add NSSCC clock and reset definitions for Qualcomm IPQ5332. > > Enable interconnect provider ability for use by the ethernet > > driver. > > > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > v5: Marked #power-domain-cells as false > > Included #interconnect-cells > > Then this might not be GCC-like clock controller or gcc.yaml > should not include power-domain-cells. qcom,gcc.yaml already doesn't mark #power-domain-cells as required, so it should be fine. See qcom,gcc-apq8064.yaml or qcom,gcc-ipq4019.yaml.
On 31/08/2024 08:56, Dmitry Baryshkov wrote: > On Sat, 31 Aug 2024 at 09:11, Krzysztof Kozlowski <krzk@kernel.org> wrote: >> >> On Thu, Aug 29, 2024 at 01:58:25PM +0530, Varadarajan Narayanan wrote: >>> From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> >>> >>> Add NSSCC clock and reset definitions for Qualcomm IPQ5332. >>> Enable interconnect provider ability for use by the ethernet >>> driver. >>> >>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> >>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> >>> --- >>> v5: Marked #power-domain-cells as false >>> Included #interconnect-cells >> >> Then this might not be GCC-like clock controller or gcc.yaml >> should not include power-domain-cells. > > qcom,gcc.yaml already doesn't mark #power-domain-cells as required, so > it should be fine. See qcom,gcc-apq8064.yaml or qcom,gcc-ipq4019.yaml. > I know, I am not saying whether code is correct or not, but whether it makes sense. If it does not have power domains, but instead interconnect cells, maybe it should not be considered a "GCC" like block. Best regards, Krzysztof
On 29.08.24 11:28, Varadarajan Narayanan wrote: > Update the GCC master/slave list to include couple of > more interfaces needed by the Network Subsystem Clock > Controller (NSSCC) > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Acked-by: Georgi Djakov <djakov@kernel.org> > --- > include/dt-bindings/interconnect/qcom,ipq5332.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/dt-bindings/interconnect/qcom,ipq5332.h b/include/dt-bindings/interconnect/qcom,ipq5332.h > index 16475bb07a48..5c08dd3c4f47 100644 > --- a/include/dt-bindings/interconnect/qcom,ipq5332.h > +++ b/include/dt-bindings/interconnect/qcom,ipq5332.h > @@ -28,6 +28,10 @@ > #define SLAVE_NSSNOC_TIMEOUT_REF 23 > #define MASTER_NSSNOC_XO_DCD 24 > #define SLAVE_NSSNOC_XO_DCD 25 > +#define MASTER_SNOC_NSSNOC_1_CLK 26 > +#define SLAVE_SNOC_NSSNOC_1_CLK 27 > +#define MASTER_SNOC_NSSNOC_CLK 28 > +#define SLAVE_SNOC_NSSNOC_CLK 29 > > #define MASTER_NSSNOC_PPE 0 > #define SLAVE_NSSNOC_PPE 1
Add bindings, driver and devicetree node for networking sub system clock controller on IPQ5332. Some of the nssnoc clocks present in GCC driver is enabled by default and its RCG is configured by bootloaders, so enable those clocks in driver probe. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- Changes in v5: - Rebased on next-20240821 - Addressed review comments - Dropped 'const qualifier' patches - Dropped 'clk: qcom: ipq5332: enable few nssnoc clocks in driver probe' - Enabled icc-clk for NSSCC - Update ICC master/slave list - In dt-bindings of nsscc Mark #power-domain-cells as false (as it is not applicable) Add #interconnect-cells - Link to v4: https://lore.kernel.org/lkml/20240122-ipq5332-nsscc-v4-0-19fa30019770@quicinc.com/ Changes in v4: - Rebased on next-20240122 - Fixed the missing space on the nsscc node - Link to v3: https://lore.kernel.org/linux-arm-msm/20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com/ Changes in v3: - Collected the tags - Dropped the dt-binding patch 3/9 - Cleaned up the header file inclusion and updated the module description in the driver - Used the decimal number instead of hex in the NSSCC node - Link to v2: https://lore.kernel.org/r/20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com Changes in v2: - Change logs are in respective patches - Link to v1: https://lore.kernel.org/r/20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com --- Kathiravan Thirumoorthy (6): dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock clk: qcom: ipq5332: add gpll0_out_aux clock dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332 arm64: dts: qcom: ipq5332: add support for the NSSCC arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332 Varadarajan Narayanan (2): dt-bindings: interconnect: Update master/slave id list clk: qcom: ipq5332: Add couple of more interconnects .../bindings/clock/qcom,ipq5332-nsscc.yaml | 64 + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5332.c | 16 + drivers/clk/qcom/nsscc-ipq5332.c | 1049 +++++++++++++++++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + .../dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++ .../dt-bindings/interconnect/qcom,ipq5332.h | 4 + 10 files changed, 1259 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-ipq5332.c create mode 100644 include/dt-bindings/clock/qcom,ipq5332-nsscc.h