mbox series

[v1,0/3] qcom: ipq5424: Add LLCC/system-cache-controller

Message ID 20241104073840.3686674-1-quic_varada@quicinc.com
Headers show
Series qcom: ipq5424: Add LLCC/system-cache-controller | expand

Message

Varadarajan Narayanan Nov. 4, 2024, 7:38 a.m. UTC 
Unlike other Qcom SoCs, IPQ5424 doesn't have multiple instances
of LLCC IP and hence doesn't have a LLCC_BROADCAST register
space, and the LLCC & LLCC_BROADCAST point to the same register
space.

Alter the driver accordingly and add the relevant entries for
enabling LLCC/system-cache-controller on the Qcom IPQ5424 SoC.

Depends On:
https://lore.kernel.org/linux-arm-msm/20241028060506.246606-1-quic_srichara@quicinc.com/

Varadarajan Narayanan (3):
  dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible
  soc: qcom: llcc: Update configuration data for IPQ5424
  arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller

 .../devicetree/bindings/cache/qcom,llcc.yaml  | 20 ++++++-
 arch/arm64/boot/dts/qcom/ipq5424.dtsi         |  7 +++
 drivers/soc/qcom/llcc-qcom.c                  | 60 +++++++++++++++++--
 3 files changed, 81 insertions(+), 6 deletions(-)


base-commit: a39230ecf6b3057f5897bc4744a790070cfbe7a8
prerequisite-patch-id: 1090fe9cee19a52dc8595e2fecef659199828246
prerequisite-patch-id: 491c9f6c32738c4eb4398962c1ae7c625cd43238
prerequisite-patch-id: 1651c75547b539eb46eb4d02630e364f262860bf
prerequisite-patch-id: 7ce54f0af6083e897067a7e5cd9561198f3d4d41
prerequisite-patch-id: 0a04fdee4b5b76cd5b734c666f7c8f5561e3e9d8
prerequisite-patch-id: 084f6dced27c39b600711dde2f797b43393cde73

Comments

Konrad Dybcio Nov. 4, 2024, 11:06 a.m. UTC | #1 
On 4.11.2024 8:38 AM, Varadarajan Narayanan wrote:
> Add a DT node for Last level cache (aka. system cache) controller
> which provides control over the last level cache present on
> IPQ5424 SoCs.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad
Rob Herring (Arm) Nov. 4, 2024, 4:19 p.m. UTC | #2 
On Mon, 04 Nov 2024 13:08:38 +0530, Varadarajan Narayanan wrote:
> Document the Last Level Cache Controller on IPQ5424. The
> 'broadcast' register space is present only in chipsets that have
> multiple instances of LLCC IP. Since IPQ5424 has only one
> instance, both the LLCC and LLCC_BROADCAST points to the same
> register space.
> 
> Hence, allow only '1' reg & reg-names entry for IPQ5424.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  .../devicetree/bindings/cache/qcom,llcc.yaml  | 20 +++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>