| Message ID | 20241116-presets-v1-0-878a837a4fee@quicinc.com |
|---|---|
| Headers | show |
| Series | PCI: dwc: Add support for configuring lane equalization presets | expand |
On 11/16/2024 4:49 PM, Konrad Dybcio wrote: > On 16.11.2024 2:37 AM, Krishna chaitanya chundru wrote: >> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >> rates used in lane equalization procedure. >> >> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> index a36076e3c56b..6a2074297030 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> phys = <&pcie6a_phy>; >> phy-names = "pciephy"; >> >> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; > > If we make all of these presets u8 arrays, we can use the: > > property = [0xff 0xff 0xff 0xff]; > > syntax > > Konrad we can't make the property as u8 as each index represents single lane and for 8 GT/s data rates each value needs 16bits. So for 8 GT/s we have to use u16 array only. - Krishna Chaitanya.
On 27.11.2024 2:42 AM, Krishna Chaitanya Chundru wrote: > > > On 11/16/2024 4:49 PM, Konrad Dybcio wrote: >> On 16.11.2024 2:37 AM, Krishna chaitanya chundru wrote: >>> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >>> rates used in lane equalization procedure. >>> >>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> index a36076e3c56b..6a2074297030 100644 >>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>> phys = <&pcie6a_phy>; >>> phy-names = "pciephy"; >>> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; >> >> If we make all of these presets u8 arrays, we can use the: >> >> property = [0xff 0xff 0xff 0xff]; >> >> syntax >> >> Konrad > we can't make the property as u8 as each index represents single lane > and for 8 GT/s data rates each value needs 16bits. So for 8 GT/s we have > to use u16 array only. In patch 4 you write them one bit at at time anyway, you can split the u16 value into 2 bytes, which will save you on some ifs down the line. Konrad
PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, read the device tree property and stores in the presets structure. Based upon the lane width and supported data rate update lane equalization registers. This patch depends on the this dt binding pull request: https://github.com/devicetree-org/dt-schema/pull/146 Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- Krishna chaitanya chundru (4): arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties PCI: of: Add API to retrieve equalization presets from device tree PCI: dwc: Improve handling of PCIe lane configuration PCI: dwc: Add support for configuring lane equalization presets arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 +++ drivers/pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 14 ++++- drivers/pci/controller/dwc/pcie-designware.h | 4 ++ drivers/pci/of.c | 62 +++++++++++++++++++++++ drivers/pci/pci.h | 17 ++++++- include/uapi/linux/pci_regs.h | 3 ++ 7 files changed, 147 insertions(+), 3 deletions(-) --- base-commit: 81983758430957d9a5cb3333fe324fd70cf63e7e change-id: 20241030-presets-ec11a3e44ab3 Best regards,