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From: Lijuan Gao <quic_lijuang@quicinc.com>
Subject: [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for
QCS615 and QCS8300
Date: Thu, 19 Dec 2024 15:59:42 +0800
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| Series |
Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300
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expand
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The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed through the GPIO framework. It is expected to be wired to the reset pin of the primary UFS memory so that the UFS driver can toggle it. The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the gpio-rangs to 134. Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> --- Changes in v2: - Update the introductory information in the cover letter - Update the commit message - Update the title of the TLMM driver patch - Link to v1: https://lore.kernel.org/r/20241212-correct_gpio_ranges-v1-0-c5f20d61882f@quicinc.com --- Lijuan Gao (6): dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615 dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300 pinctrl: qcom: correct the ngpios entry for QCS615 pinctrl: qcom: correct the ngpios entry for QCS8300 arm64: dts: qcom: correct gpio-ranges for QCS615 arm64: dts: qcom: correct gpio-ranges for QCS8300 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +- Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- drivers/pinctrl/qcom/pinctrl-qcs615.c | 2 +- drivers/pinctrl/qcom/pinctrl-qcs8300.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) --- base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07 change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7 Best regards,