From patchwork Thu Jan 2 11:30:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 854766 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0144E1AC44D; Thu, 2 Jan 2025 11:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735817468; cv=none; b=Ze0l5EDnTbVg7Ip15zcvNYzRErfKp1Z6tWpkHi188S+y/d75IXGEMmZgN+8BMuhqDM4+JGEAHSmdvNJFmeJAQmGkWPERG0pUzh4nsb/fe99eais1MtwVmSWJnZ+7cDNEcICt+jvBb8qK2ZTteSHOI+6s2KA/uePEP1wiOCcd8eY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735817468; c=relaxed/simple; bh=XAJnOHONzPk2PXr+e3diSZUglZMCnNbpGFh4+iXZwA0=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=betyLHcC6Kw4XElSf0t2FZF2d/eGDe0XAWAmD6b7uBuGQtLzX6GZUPCpaPeChXxB9HBqsxoXUbde9AC/Vpn7M6lq1A+h+rYBgqBIalpEmA7IIP/Mbu3gZmdspHrDrWzBnxW0f1sJYqqHgy7s4zIiofWKYpQcyy8yJcZSvA1JH4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=dwDsTI+f; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="dwDsTI+f" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5020rVJP020443; Thu, 2 Jan 2025 11:30:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=zJCJH9RvhZoRLeRJbOciMG B2dbez7BtmrjqwU8gvjtM=; b=dwDsTI+fHxkTy5dXtPEdyAu5B5rstcYpwrHnWv ICH2iQqpvV0Jk6d7K/RJqXTUyeDgO3+LPwDyFvjR6Svb98hdRUF3YbYUZ+/VMkcx 6s1titz04HiGYAZKcYnGJ7D4IM4y08BFj+mPg8VeuTmho2Q/yuUvTbzi3vlcLqqQ cTscprCy+LaQHlrHHzNch5C6hP6kMRsyM1s3ayghpNJVuUPGhpZVaI0P5i4EkJeo aHABTZrhIB8w+Lopio6voeUwToSZqLl8RHbRaE5HntktKI1DcvFrdchVLbU5kDYx fDIvNU5erJ4NgHMY4dR+IAyHR8GO7QiyiseJLJLmPKcBeBiA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43wgnj140b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jan 2025 11:30:44 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 502BUibp007919 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 2 Jan 2025 11:30:44 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 2 Jan 2025 03:30:38 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 0/5] Add PCIe support for Qualcomm IPQ5332 Date: Thu, 2 Jan 2025 17:00:14 +0530 Message-ID: <20250102113019.1347068-1-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1vqwo_Fbd_B62m8PNIO5f1K99BqzSVYo X-Proofpoint-GUID: 1vqwo_Fbd_B62m8PNIO5f1K99BqzSVYo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501020099 Patch series adds support for enabling the PCIe controller and UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and PCIe1 is Gen3 X2 are added. This series combines [1] and [2]. [1] introduces IPQ5018 PCIe support and [2] depends on [1] to introduce IPQ5332 PCIe support. Since the community was interested in [2] (please see [3]), tried to revive IPQ5332's PCIe support with v2 of this patch series. v2 of this series pulled in the phy driver from [1] tried to address comments/feedback given in both [1] and [2]. 1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ 2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/ 3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/ v5: phy bindings: * Drop '3x1' & '3x2' from compatible string * Use 'num-lanes' to differentiate instead of '3x1' or '3x2' in compatible string * Describe clocks and resets instead of just maxItems phy driver: * Get num-lanes from DTS * Drop compatible specific init data as there is only one compatible string controller bindings: * Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts dtsi: * Add 'num-lanes' to "pcie1_phy: phy@4b1000" * Make ipq5332 as main and ipq9574 as fallback compatible * Sort controller nodes per address misc: Add R-B tag from Konrad to dts and dtsi patches v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings * phy bindings - Remove reset-names as the resets are handled with bulk APIs * phy bindings - Fix order in the 'required' section * phy bindings - Remove clock-output-names * dtsi - Add missing reset for pcie1_phy * dtsi - Convert 'reg-names' to a vertical list * dts - Fix nodes sort order * dts - Use property-n followed by property-names v3: * Update the cover letter with the sources of the patches * Rename the dt-bindings yaml file similar to other phys * Drop ipq5332 specific pcie controllor bindings and reuse ipq9574 pcie controller bindings for ipq5332 * Please see patches for specific changes * Set GPL license for phy-qcom-uniphy-pcie-28lp.c v2: Address review comments from V1 Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c) Include phy driver from the dependent series v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/ Nitheesh Sekar (2): dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy phy: qcom: Introduce PCIe UNIPHY 28LP driver Praveenkumar I (2): arm64: dts: qcom: ipq5332: Add PCIe related nodes arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Varadarajan Narayanan (1): dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller .../devicetree/bindings/pci/qcom,pcie.yaml | 10 +- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 71 +++++ arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 221 +++++++++++++- drivers/phy/qualcomm/Kconfig | 12 + drivers/phy/qualcomm/Makefile | 1 + .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 287 ++++++++++++++++++ 7 files changed, 674 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2