| Message ID | 20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org |
|---|---|
| Headers | show |
| Series | PCI: dwc: Add PTM sysfs support | expand |
On Tue, Feb 18, 2025 at 06:31:02PM +0200, Dmitry Baryshkov wrote: > On Tue, Feb 18, 2025 at 08:06:40PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > Since these are common to all Desginware PCIe IPs, move them to a new > > header, 'pcie-dwc.h' so that other drivers could make use of them. > > Which drivers are going to use it? Please provide an explanation. > I can certainly add reference as 'upcoming pcie-designware-sysfs' driver. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > MAINTAINERS | 1 + > > drivers/perf/dwc_pcie_pmu.c | 23 ++--------------------- > > include/linux/pcie-dwc.h | 34 ++++++++++++++++++++++++++++++++++ > > 3 files changed, 37 insertions(+), 21 deletions(-) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 896a307fa065..b4d09d52a750 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -18123,6 +18123,7 @@ S: Maintained > > F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml > > F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > F: drivers/pci/controller/dwc/*designware* > > +F: include/linux/pcie-dwc.h > > > > PCI DRIVER FOR TI DRA7XX/J721E > > M: Vignesh Raghavendra <vigneshr@ti.com> > > diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c > > index cccecae9823f..05b37ea7cf16 100644 > > --- a/drivers/perf/dwc_pcie_pmu.c > > +++ b/drivers/perf/dwc_pcie_pmu.c > > @@ -13,6 +13,7 @@ > > #include <linux/errno.h> > > #include <linux/kernel.h> > > #include <linux/list.h> > > +#include <linux/pcie-dwc.h> > > #include <linux/perf_event.h> > > #include <linux/pci.h> > > #include <linux/platform_device.h> > > @@ -99,26 +100,6 @@ struct dwc_pcie_dev_info { > > struct list_head dev_node; > > }; > > > > -struct dwc_pcie_pmu_vsec_id { > > - u16 vendor_id; > > - u16 vsec_id; > > - u8 vsec_rev; > > -}; > > - > > -/* > > - * VSEC IDs are allocated by the vendor, so a given ID may mean different > > - * things to different vendors. See PCIe r6.0, sec 7.9.5.2. > > - */ > > -static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = { > > - { .vendor_id = PCI_VENDOR_ID_ALIBABA, > > - .vsec_id = 0x02, .vsec_rev = 0x4 }, > > - { .vendor_id = PCI_VENDOR_ID_AMPERE, > > - .vsec_id = 0x02, .vsec_rev = 0x4 }, > > - { .vendor_id = PCI_VENDOR_ID_QCOM, > > - .vsec_id = 0x02, .vsec_rev = 0x4 }, > > - {} /* terminator */ > > -}; > > - > > static ssize_t cpumask_show(struct device *dev, > > struct device_attribute *attr, > > char *buf) > > @@ -529,7 +510,7 @@ static void dwc_pcie_unregister_pmu(void *data) > > > > static u16 dwc_pcie_des_cap(struct pci_dev *pdev) > > { > > - const struct dwc_pcie_pmu_vsec_id *vid; > > + const struct dwc_pcie_vsec_id *vid; > > u16 vsec; > > u32 val; > > > > diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h > > new file mode 100644 > > index 000000000000..261ae11d75a4 > > --- /dev/null > > +++ b/include/linux/pcie-dwc.h > > @@ -0,0 +1,34 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2021-2023 Alibaba Inc. > > + * > > + * Copyright 2025 Linaro Ltd. > > + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > + */ > > + > > +#ifndef LINUX_PCIE_DWC_H > > +#define LINUX_PCIE_DWC_H > > + > > +#include <linux/pci_ids.h> > > + > > +struct dwc_pcie_vsec_id { > > + u16 vendor_id; > > + u16 vsec_id; > > + u8 vsec_rev; > > +}; > > + > > +/* > > + * VSEC IDs are allocated by the vendor, so a given ID may mean different > > + * things to different vendors. See PCIe r6.0, sec 7.9.5.2. > > + */ > > +static const struct dwc_pcie_vsec_id dwc_pcie_pmu_vsec_ids[] = { > > Having it in the header means that there are going to be several > copies of this data. Is that expected? > Yes. I wanted to consolidate these ids in a single file to make it easy to track them. Otherwise, these are spread across different subsystems, making it harder to maintain. - Mani
Hi, This series adds sysfs support for PCIe PTM in Synopsys Designware IPs. First patch moves the common DWC struct definitions (dwc_pcie_vsec_id) to include/pci/pcie-dwc.h from dwc-pcie-pmu driver. This allows reusing the same definitions in pcie-designware-sysfs driver introduced in this series and also in the debugfs series by Shradha [1]. Second patch adds support for searching the Vendor Specific Extended Capability (VSEC) in the pcie-designware driver. This patch was originally based on Shradha's patch [2], but modified to accept 'struct dwc_pcie_vsec_id' to avoid iterating through the vsec_ids in the driver. Third patch adds the actual sysfs support for PTM in a new file pcie-designware-sysfs.c built along with pcie-designware.c. Finally, fourth patch masks the PTM_UPDATING interrupt in the pcie-qcom-ep driver to avoid processing the interrupt for each PTM context update. Testing ======= This series is tested on Qcom SA8775p Ride Mx platform where one SA8775p acts as RC and another as EP with following instructions: RC -- $ echo 1 > /sys/devices/platform/1c10000.pcie/dwc/ptm/ptm_context_valid EP -- $ echo auto > /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_context_update $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_local_clock 159612570424 $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_master_clock 159609466232 $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_t1 159609466112 $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_t4 159609466518 NOTE: To make use of the PTM feature, the host PCIe client driver has to call 'pci_enable_ptm()' API during probe. This series was tested with enabling PTM in the MHI host driver with a local change (which will be upstreamed later). Technically, PTM could also be enabled in the pci_endpoint_test driver, but I didn't add the change as I'm not sure we'd want to add random PCIe features in the test driver without corresponding code in pci-epf-test driver. Merging Strategy ================ I'd like to have an ACK from the perf maintainers to take the whole series through PCI tree. [1] https://lore.kernel.org/linux-pci/20250214105007.97582-1-shradha.t@samsung.com [2] https://lore.kernel.org/linux-pci/20250214105007.97582-2-shradha.t@samsung.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Manivannan Sadhasivam (4): perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h' PCI: dwc: Add helper to find the Vendor Specific Extended Capability (VSEC) PCI: dwc: Add sysfs support for PTM PCI: qcom-ep: Mask PTM_UPDATING interrupt Documentation/ABI/testing/sysfs-platform-dwc-pcie | 70 ++++++ MAINTAINERS | 2 + drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 3 + drivers/pci/controller/dwc/pcie-designware-host.c | 4 + drivers/pci/controller/dwc/pcie-designware-sysfs.c | 278 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 46 ++++ drivers/pci/controller/dwc/pcie-designware.h | 22 ++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 8 + drivers/perf/dwc_pcie_pmu.c | 23 +- include/linux/pcie-dwc.h | 42 ++++ 11 files changed, 478 insertions(+), 22 deletions(-) --- base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b change-id: 20250218-pcie-qcom-ptm-bf6952f5c4e5 Best regards,