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[v4,0/2] arm64: dts: qcom: sm8650: switch to 4 interrupt cells to add PPI partitions for PMUs

Message ID 20250228-topic-sm8650-pmu-ppi-partition-v4-0-78cffd35c73d@linaro.org
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Series arm64: dts: qcom: sm8650: switch to 4 interrupt cells to add PPI partitions for PMUs | expand

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Neil Armstrong Feb. 28, 2025, 8:40 a.m. UTC 
Swich to 4 interrupt cells on the GIC node to allow us passing
the proper PPI interrupt partitions for the ARM PMUs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Changes in v4:
- Drop PMU irq flag change, Stephan digged and PPI have fixed polarity and PMU is hardcoded to low
 => https://lore.kernel.org/all/Z8Cza7ZZxy3fbBC9@linaro.org/
- Link to v3: https://lore.kernel.org/r/20250227-topic-sm8650-pmu-ppi-partition-v3-0-0f6feeefe50f@linaro.org

Changes in v3:
- Add a patch changing the interrupt polarity, thx for dmitry
- Link to v2: https://lore.kernel.org/r/20250227-topic-sm8650-pmu-ppi-partition-v2-0-b93006a65037@linaro.org

Changes in v2:
- Added Konrad's reviews
- Rebased on linux-next
- Link to v1: https://lore.kernel.org/r/20250207-topic-sm8650-pmu-ppi-partition-v1-0-dd3ba17b3eea@linaro.org

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Neil Armstrong (2):
      arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions
      arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs

 arch/arm64/boot/dts/qcom/sm8650.dtsi | 556 ++++++++++++++++++-----------------
 1 file changed, 285 insertions(+), 271 deletions(-)
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base-commit: 0e2a500eff87c710f3947926e274fd83d0cabb02
change-id: 20250207-topic-sm8650-pmu-ppi-partition-1e9df8b877da

Best regards,