mbox series

[v2,0/4] Add CMN PLL clock controller support for IPQ5424

Message ID 20250411-qcom_ipq5424_cmnpll-v2-0-7252c192e078@quicinc.com
Headers show
Series Add CMN PLL clock controller support for IPQ5424 | expand

Message

Luo Jie April 11, 2025, 12:58 p.m. UTC 
The CMN PLL block of IPQ5424 is almost same as that of IPQ9574
which is currently supported by the driver. The only difference
is that the fixed output clocks to NSS and PPE from CMN PLL have
a different clock rate. In IPQ5424, the output clocks are supplied
to NSS at 300 MHZ and to PPE at 375 MHZ.

This patch series extends the CMN PLL driver to support IPQ5424.
It also adds the SoC specific header file to export the CMN PLL
output clock specifiers for IPQ5424. The new table of output
clocks is added for the CMN PLL of IPQ5424, which is acquired
from the device according to the compatible.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
Changes in v2:
- Alphanumeric order for the compatible strings in dtbindings.
- Add the IPQ5424 SoC specific header file to export the clock specifiers.
- Drop the comma of the sentinel entry of the output clock array.
- Add Reviewed-by tag on the DTS patches.
- Link to v1: https://lore.kernel.org/r/20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com

---
Luo Jie (4):
      dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
      clk: qcom: cmnpll: Add IPQ5424 SoC support
      arm64: dts: ipq5424: Add CMN PLL node
      arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock

 .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       |  1 +
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts        | 23 ++++++++++++--
 arch/arm64/boot/dts/qcom/ipq5424.dtsi              | 27 ++++++++++++++++-
 drivers/clk/qcom/ipq-cmn-pll.c                     | 35 ++++++++++++++++++----
 include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h   | 22 ++++++++++++++
 5 files changed, 100 insertions(+), 8 deletions(-)
---
base-commit: 01c6df60d5d4ae00cd5c1648818744838bba7763
change-id: 20250411-qcom_ipq5424_cmnpll-960a8f597033

Best regards,

Comments

Rob Herring April 11, 2025, 8:59 p.m. UTC | #1 
On Fri, 11 Apr 2025 20:58:10 +0800, Luo Jie wrote:
> The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
> input clock. The output clocks are the same as IPQ9574 SoC, except
> for the clock rate of output clocks to PPE and NSS.
> 
> Also, add the new header file to export the CMN PLL output clock
> specifiers for IPQ5424 SoC.
> 
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       |  1 +
>  include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h   | 22 ++++++++++++++++++++++
>  2 files changed, 23 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>