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Fri, 25 Apr 2025 09:29:59 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 53P9TxMn022122; Fri, 25 Apr 2025 09:29:59 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 53P9TxSq022121 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Apr 2025 09:29:59 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id E057240D6C; Fri, 25 Apr 2025 17:29:57 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com, quic_wenbyao@quicinc.com Subject: [PATCH v2 0/4] arm64: qcom: x1e80100-qcp: Add power supply and sideband signals for PCIe RC Date: Fri, 25 Apr 2025 17:29:51 +0800 Message-Id: <20250425092955.4099677-1-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=EtLSrTcA c=1 sm=1 tr=0 ts=680b561a cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=4-n6rLelgxkyzdg-Py0A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: r63uoIcIo8vJDo1FizADCv02yM4f4dqb X-Proofpoint-ORIG-GUID: r63uoIcIo8vJDo1FizADCv02yM4f4dqb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDA2OCBTYWx0ZWRfX7R6Yb3LKeNoi 5sSX6JFZRKr+/obqun0INO96Qjkay+dnTqRwO0CEaw2MR1jkz/IUWD2TFCHvMb6Ub9b9hP9ML2c nC5XhbLPG/WAse+IUbA6aPsQ5KDpuTEzLSt9waTdb9cCTD27zbUGS3i+W3YDkd9yl7ElUn8nO1Q 5uCITYs7nic0mwv5R8zFlgxGRSZnR7pk3puC6IWWdqT/zWTdM0uFemLnxTLXVVz7552Pk9IYgJc g2Uknix92kM4W+nU2/5pIKiIRWcK4urH+Ou2m4xW8E70zTYaxyFHehzbR/zaIBzNIuSjcuvGEFQ P9zVNZ22FTO6ywI2KfZitsN3IgDk4MY/Ea0KKQkRwhnzQ4ws71Jep1nRMNy1MNdvHfC00T1CuOj AcjbSdhf27KvjfdDNghTX9t6d9074AOaAv/sw4cpxbw9eXcn0yp1QlIlZZFqd07MkRypLevG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 mlxscore=0 clxscore=1015 spamscore=0 mlxlogscore=816 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250068 The first patch enables the PCI Power Control driver to control the power state of PCI slots. The second patch adds the bus topology of PCIe domain 3 on x1e80100 platform. The third patch adds perst, wake and clkreq sideband signals, and describe the regulators powering the rails of the PCI slots in the devicetree for PCIe3 controller and PHY device. The fourth patch adds qref supply for PCIe PHYs. The patchset has been modified based on comments and suggestions. Changes in v2: - Select PCI_PWRCTL_SLOT by ARCH_QCOM in arch/arm64/Kconfig.platforms in Patch 1/4. - Add an empty line before pcie3port node in Patch 2/4. - Rename regulator-pcie_12v regulator-pcie_3v3_aux and regulator-pcie_3v3 in Patch 3/4. - Add Patch 4/4 to describe qref supply of PCIe PHYs. - Link to v1: https://lore.kernel.org/all/20250320055502.274849-1-quic_wenbyao@quicinc.com/ Qiang Yu (4): arm64: Kconfig: enable PCI Power Control Slot driver for QCOM arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP arm64: dts: qcom: x1e80100-qcp: Add qref supply for PCIe PHYs arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 121 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++ 3 files changed, 133 insertions(+) base-commit: bc8aa6cdadcc00862f2b5720e5de2e17f696a081 prerequisite-patch-id: 8d8c88ca71e145f5f1c5145d9ff3ebe90101aab7 Reviewed-by: Konrad Dybcio