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Thu, 08 May 2025 08:15:31 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5488FV2t015199; Thu, 8 May 2025 08:15:31 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 5488FUvP015198 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 May 2025 08:15:31 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id CBF9540CFD; Thu, 8 May 2025 16:15:28 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com, quic_wenbyao@quicinc.com Subject: [PATCH v3 0/5] arm64: qcom: x1e80100-qcp: Add power supply and sideband signals for PCIe RC Date: Thu, 8 May 2025 16:15:09 +0800 Message-Id: <20250508081514.3227956-1-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA4MDA3MiBTYWx0ZWRfX9Rl2cXH2JA+e gS5hPybH3+FlvOLrpRNHOJiFwppLc9Y+i5+X2nD3jcXQDEyntulxKHq89z1t5nZldbdNuwoZJfD MgY+5wZELbGcakg9zSeZtWKOYCn1pJfSETexwEv1VZ7GmjnpmUXBS1wD7e8Afe/s9rIPL93RXmE hNFMdO03CqKHYi1PL1TcuiQ5gNDEHsSRbjGJM51dcITZ7bjRoYbg966jC2FlNHtWXl8gijEPNUu LvuxRlfcB/zDmYwqj7kulMseHOMZkKPWHaOyzRgHgtSMMBzefPZ17svWK/Y43y29gIInAy1zskq BSAwd6H6hUsLDt+8g0efBs7uEz4urD9O30UlgbLgq2Wc1lhp6RgQAIbkUAmEZYz67KzQMTFZ91P 38+i1IGPxU6O9iwWS3U8bywyIMg0R9qYhqCTLKyaolHJYfGQ3Ai2CbG+B1DblqmbaPDE0rU6 X-Proofpoint-ORIG-GUID: dxZEV0NnWuBV0HwtqCE43qcJprTz0pQm X-Proofpoint-GUID: dxZEV0NnWuBV0HwtqCE43qcJprTz0pQm X-Authority-Analysis: v=2.4 cv=Yt4PR5YX c=1 sm=1 tr=0 ts=681c6826 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=gQCXtSsaVPIGO4BefbEA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-08_02,2025-05-07_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 adultscore=0 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=872 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505080072 The first patch enables the PCI Power Control driver to control the power state of PCI slots. The second patch adds the bus topology of PCIe domain 3 on x1e80100 platform. The third patch adds perst, wake and clkreq sideband signals, and describe the regulators powering the rails of the PCI slots in the devicetree for PCIe3 controller and PHY device. The fourth patch adds qref supply in dts nodes of PCIe PHYs. The fifth patch requests qref supply for PCIe PHYs. The patchset has been modified based on comments and suggestions. Changes in v3: - Replace PCI_PWRCTL_SLOT with PCI_PWRCTRL_SLOT in Patch 1/5. - Kepp the order of pinctrl-0 before pinctrl-names in Patch 3/5. - Add Patch 5/5 to request qref supply for PCIe PHYs. - Link to v2: https://lore.kernel.org/all/20250425092955.4099677-1-quic_wenbyao@quicinc.com/ Changes in v2: - Select PCI_PWRCTL_SLOT by ARCH_QCOM in arch/arm64/Kconfig.platforms in Patch 1/4. - Add an empty line before pcie3port node in Patch 2/4. - Rename regulator-pcie_12v regulator-pcie_3v3_aux and regulator-pcie_3v3 in Patch 3/4. - Add Patch 4/4 to describe qref supply of PCIe PHYs. - Link to v1: https://lore.kernel.org/all/20250320055502.274849-1-quic_wenbyao@quicinc.com/ Qiang Yu (5): arm64: Kconfig: enable PCI Power Control Slot driver for QCOM arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP arm64: dts: qcom: x1e80100-qcp: Add qref supply for PCIe PHYs phy: qcom: qmp-pcie: add x1e80100 qref supplies arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 121 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 37 ++++++- 4 files changed, 165 insertions(+), 5 deletions(-) base-commit: 0a00723f4c2d0b273edd0737f236f103164a08eb