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From: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com,
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Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
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Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Subject: [PATCH v2 0/2] Add Equalization Settings for 8.0 GT/s and Add PCIe
Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s
Date: Wed, 11 Jun 2025 18:03:17 +0800
Message-Id: <20250611100319.464803-1-quic_ziyuzhan@quicinc.com>
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|
| Series |
Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s
|
expand
|
This series adds add equalization settings for 8.0 GT/s, and add PCIe lane equalization preset properties for 8.0 GT/s and 16.0 GT/s for sa8775p ride platform, which fix AER errors. While equalization settings for 16 GT/s have already been set, this update adds the required equalization settings for PCIe operating at 8.0 GT/s, including the configuration of shadow registers, ensuring optimal performance and stability. The DT change for sa8775p add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Changes in v2: - Update code in pcie-qcom-common.c make it easier to read. (Neil) - Fix the compile error. - Link to v1: https://lore.kernel.org/all/20250604091946.1890602-1-quic_ziyuzhan@quicinc.com Ziyue Zhang (2): PCI: qcom: Add equalization settings for 8.0 GT/s arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++ drivers/pci/controller/dwc/pcie-designware.h | 1 - drivers/pci/controller/dwc/pcie-qcom-common.c | 60 +++++++++++-------- drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +- drivers/pci/controller/dwc/pcie-qcom.c | 6 +- 6 files changed, 49 insertions(+), 32 deletions(-) base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494