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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:04:43 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Date: Tue, 24 Jun 2025 14:04:28 +0800 Message-Id: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=YYu95xRf c=1 sm=1 tr=0 ts=685a3ffd cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=nBcv9sv72UtkhE4thMQA:9 a=GvdueXVYPmCkWapjIL-Q:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: TN_WIqT-jExrNSHgC7shhSM3f0zN1td9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MCBTYWx0ZWRfX67dg0nAu+af8 JKw8eT72BjCL1lY8mJc0ZTq+Q3YzaHE7RPPQ5FpVpy35J23iN67XoXDsV6rhY6q2VKZ4jVravCr wVApbKYRWCWPDp2jvVBTBUsFgiXWCNZ0WGO9banBQkmMxlWhA2owlhubwrzcvdrPAg1wzW4o4bO 33R4XqLEGPcZC/22z2hjBsiwi6LFMuISdttyM9jh36WlPJwgQGyPq1drB/rNWAjRqgoCe1lbmLU NGFU8K1q1sO7Bv3Po1oM/AZvka9dzTA6FuRC3vHY0Qspu1uINP4mgCozHsD9oAPrNEr7WmiCXZB jYj64pqzu94LIE6ZLGVdOA2z8fYvOvXAIAoXOob8PNE9gRcJfPgIcV+kea6EkclHTKttCKsZqmF W0wtPT0+WSjAfDCHMMLFYPevaUP6eyn6Z846hkUek7Sgv4ETtGEi9pCli1xMuXveAXeNVcbJ X-Proofpoint-ORIG-GUID: TN_WIqT-jExrNSHgC7shhSM3f0zN1td9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240050 The byte-cntr function provided by the CTCU device is used to count the trace data entering the ETR. An interrupt is tiggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions. Based on this concept, the irq_cnt can be used to determine whether the etr_buf is full. The ETR device will be disabled when the active etr_buf is nearly full or a timeout occurs. The nearly full buffer will be switched to background after synced. A new buffer will be picked from the etr_buf_list, then restart the ETR device. The byte-cntr reading functions can access data from the synced and deactivated buffer, transferring trace data from the etr_buf to userspace without stopping the ETR device. The byte-cntr read operation has integrated with the file node tmc_etr, e.g. /dev/tmc_etr0 /dev/tmc_etr1 There are two scenarios for the tmc_etr file node with byte-cntr function: 1. BYTECNTRVAL register is configured and byte-cntr is enabled -> byte-cntr read 2. BYTECNTRVAL register is reset or byte-cntr is disabled -> original behavior Shell commands to enable byte-cntr reading for etr0: echo 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_val echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink echo 1 > /sys/bus/coresight/devices/etm0/enable_source cat /dev/tmc_etr0 Reset the BYTECNTR register for etr0: echo 0 > /sys/bus/coresight/devices/ctcu0/irq_val Changes in V3: 1. The previous solution has been deprecated. 2. Add a etr_buf_list to manage allcated etr buffers. 3. Add a logic to switch buffer for ETR. 4. Add read functions to read trace data from synced etr buffer. Link to V2 - https://lore.kernel.org/all/20250410013330.3609482-1-jie.gan@oss.qualcomm.com/ Changes in V2: 1. Removed the independent file node /dev/byte_cntr. 2. Integrated the byte-cntr's file operations with current ETR file node. 3. Optimized the driver code of the CTCU that associated with byte-cntr. 4. Add kernel document for the export API tmc_etr_get_rwp_offset. 5. Optimized the way to read the rwp_offset according to Mike's suggestion. 6. Removed the dependency of the dts patch. Link to V1 - https://lore.kernel.org/all/20250310090407.2069489-1-quic_jiegan@quicinc.com/ Jie Gan (10): coresight: core: Refactoring ctcu_get_active_port and make it generic coresight: core: add a new API to retrieve the helper device dt-bindings: arm: add an interrupt property for Coresight CTCU coresight: ctcu: enable byte-cntr for TMC ETR devices coresight: tmc: add etr_buf_list to store allocated etr_buf coresight: tmc: add create/delete functions for etr_buf_node coresight: tmc: add prepare/unprepare functions for byte-cntr coresight: tmc: add a switch buffer function for byte-cntr coresight: tmc: add read function for byte-cntr arm64: dts: qcom: sa8775p: Add interrupts to CTCU device .../testing/sysfs-bus-coresight-devices-ctcu | 5 + .../bindings/arm/qcom,coresight-ctcu.yaml | 17 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 + drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 54 ++++ .../coresight/coresight-ctcu-byte-cntr.c | 102 +++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 113 ++++++-- drivers/hwtracing/coresight/coresight-ctcu.h | 52 +++- drivers/hwtracing/coresight/coresight-priv.h | 4 + .../hwtracing/coresight/coresight-tmc-core.c | 70 ++++- .../hwtracing/coresight/coresight-tmc-etr.c | 270 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 29 ++ 12 files changed, 691 insertions(+), 32 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c