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[78.144.123.164]) by mx.google.com with ESMTPSA id ez5sm3080157wjd.9.2014.05.16.12.45.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 May 2014 12:45:47 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: agross@quicinc.com Cc: linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH RFC 1/4] ARM: DT: QCOM: apq8064: fix the memory range for sdcc node. Date: Fri, 16 May 2014 20:45:43 +0100 Message-Id: <1400269543-15449-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400269500-15408-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400269500-15408-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla This patch fixes the range of iomemory for sdcc controller, it is now set to 0x2000 so that the mmci driver could talk to dml hardware as well. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 640fb1d..2a6cd09 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -167,7 +167,7 @@ status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; + reg = <0x12400000 0x2000>; interrupts = ; interrupt-names = "cmd_irq"; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; @@ -184,7 +184,7 @@ compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; - reg = <0x12180000 0x8000>; + reg = <0x12180000 0x2000>; interrupts = ; interrupt-names = "cmd_irq"; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;