From patchwork Fri Mar 20 20:21:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 46165 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f72.google.com (mail-la0-f72.google.com [209.85.215.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id EDA7921418 for ; Fri, 20 Mar 2015 20:24:08 +0000 (UTC) Received: by labgm9 with SMTP id gm9sf19206939lab.1 for ; Fri, 20 Mar 2015 13:24:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=7QnLhdwZZdmylBlbtxO2/u3OMF1hdRzg4BPKbX6EFL0=; b=AN/1wZ3P3fgq5XXmkJsPUMypoMcDmWmluBeFHpRdqoRtDhpSPXq3EshVJAFNCqN/Bl T6B/WDqnlzFfdT9jdjPAXojsBHiyTp+r3dMgJ3IhGzWc/wuNU0jra4BuR2MjQy7XlqWN ps9Vm2RzL/Nf1F2tk6Cb6cXPCkPG5z7LusiKyl5z202P1gdtBKvfsSlYF533w2xyMPYZ BUemoYkkm21VbySxFzwLe8W++xx8/rNj0O36XTNCw2OePb16fRyaTtWZbDubDMWvDNOB I8robtCO4SNdTTf+qHXVokRe9NMfY0j22lhCR7efijo83QxQ9jpOE9IafC/duRcSdDjJ GJiw== X-Gm-Message-State: ALoCoQl+yZ+W9y+7cbV0w4euJTbN151jLIAtaoIVtyrC1XA+6Nllwc3ogxfEVOURvp4SfwOrNRLi X-Received: by 10.152.28.137 with SMTP id b9mr13437051lah.8.1426883047923; Fri, 20 Mar 2015 13:24:07 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.37.162 with SMTP id z2ls326553laj.75.gmail; Fri, 20 Mar 2015 13:24:07 -0700 (PDT) X-Received: by 10.112.212.106 with SMTP id nj10mr55476723lbc.36.1426883047565; Fri, 20 Mar 2015 13:24:07 -0700 (PDT) Received: from mail-la0-f44.google.com (mail-la0-f44.google.com. [209.85.215.44]) by mx.google.com with ESMTPS id w5si3818538lad.119.2015.03.20.13.24.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Mar 2015 13:24:07 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) client-ip=209.85.215.44; Received: by labe2 with SMTP id e2so20346376lab.3 for ; Fri, 20 Mar 2015 13:24:07 -0700 (PDT) X-Received: by 10.112.55.103 with SMTP id r7mr2662778lbp.29.1426883047287; Fri, 20 Mar 2015 13:24:07 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.35.133 with SMTP id h5csp269074lbj; Fri, 20 Mar 2015 13:24:06 -0700 (PDT) X-Received: by 10.66.123.110 with SMTP id lz14mr96337382pab.30.1426882732216; Fri, 20 Mar 2015 13:18:52 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id yo1si11295863pac.65.2015.03.20.13.18.51; Fri, 20 Mar 2015 13:18:52 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751305AbbCTUSk (ORCPT + 5 others); Fri, 20 Mar 2015 16:18:40 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:33433 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751131AbbCTUSi (ORCPT ); Fri, 20 Mar 2015 16:18:38 -0400 Received: by pabxg6 with SMTP id xg6so106129490pab.0 for ; Fri, 20 Mar 2015 13:18:37 -0700 (PDT) X-Received: by 10.66.66.196 with SMTP id h4mr189015500pat.127.1426882717595; Fri, 20 Mar 2015 13:18:37 -0700 (PDT) Received: from ubuntu.localdomain (i-global254.qualcomm.com. [199.106.103.254]) by mx.google.com with ESMTPSA id ji6sm9543280pac.30.2015.03.20.13.18.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Mar 2015 13:18:37 -0700 (PDT) From: Lina Iyer To: daniel.lezcano@linaro.org, khilman@linaro.org, sboyd@codeaurora.org, galak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: lorenzo.pieralisi@arm.com, msivasub@codeaurora.org, devicetree@vger.kernel.org, agross@codeaurora.org, Lina Iyer Subject: [PATCH v17 09/10] ARM: dts: qcom: Add idle state device nodes for 8064 Date: Fri, 20 Mar 2015 14:21:16 -0600 Message-Id: <1426882877-33008-10-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1426882877-33008-1-git-send-email-lina.iyer@linaro.org> References: <1426882877-33008-1-git-send-email-lina.iyer@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lina.iyer@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add ARM common idle state device bindings for cpuidle support for APQ 8064. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Cc: Kumar Gala Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 9fd24bc..592e985 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -23,6 +23,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -33,6 +34,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -43,6 +45,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -53,12 +56,23 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; }; cpu-pmu {