From patchwork Tue Jan 7 21:04:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 190750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2066DC282DD for ; Tue, 7 Jan 2020 21:19:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DA18F2072A for ; Tue, 7 Jan 2020 21:19:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="MU31/cwR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728629AbgAGVTb (ORCPT ); Tue, 7 Jan 2020 16:19:31 -0500 Received: from mail25.static.mailgun.info ([104.130.122.25]:55010 "EHLO mail25.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729088AbgAGVEu (ORCPT ); Tue, 7 Jan 2020 16:04:50 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1578431089; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=n/ycW8qiMK9GlVy2FuLC/bLDbpf71fSQ4+N714rzFo4=; b=MU31/cwRKN75h7LnQMUG6iU4XRwz6lIA4Y4tYZQnm0ArX8Hyjqg9673J4ANnVFrq4IxSUoUp JPlqUh8s4dU7ayQyDJE2fSuRsZN9A68a7D6RQKBbk2ZqgcKTIxo/qFWe0doksWSyde3GZoEk JtUqEJriZ3StvSl/lQE66EYFBnE= X-Mailgun-Sending-Ip: 104.130.122.25 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e14f26d.7fd22cad6228-smtp-out-n03; Tue, 07 Jan 2020 21:04:45 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 5D037C447AB; Tue, 7 Jan 2020 21:04:44 +0000 (UTC) Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman) by smtp.codeaurora.org (Postfix) with ESMTPSA id 601D9C447A9; Tue, 7 Jan 2020 21:04:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 601D9C447A9 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: Bjorn Andersson , agross@kernel.org, swboyd@chromium.org, Stephan Gerhold Cc: Elliot Berman , saiprakash.ranjan@codeaurora.org, tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, Brian Masney , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/17] firmware: qcom_scm-32: Use SMC arch wrappers Date: Tue, 7 Jan 2020 13:04:18 -0800 Message-Id: <1578431066-19600-10-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578431066-19600-1-git-send-email-eberman@codeaurora.org> References: <1578431066-19600-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use SMC arch wrappers instead of inline assembly. Change-Id: Ia8b8518f842462eb3f7e0d3200497431ca9c2c4e Tested-by: Brian Masney # arm32 Tested-by: Stephan Gerhold Signed-off-by: Elliot Berman --- drivers/firmware/Makefile | 1 - drivers/firmware/qcom_scm-32.c | 71 ++++++++++-------------------------------- 2 files changed, 17 insertions(+), 55 deletions(-) diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 3fcb919..747fb73 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o obj-$(CONFIG_QCOM_SCM) += qcom_scm.o obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o -CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 8b57240..362d042 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "qcom_scm.h" @@ -121,25 +122,13 @@ static inline void *scm_legacy_get_response_buffer( static u32 __scm_legacy_do(u32 cmd_addr) { int context_id; - register u32 r0 asm("r0") = 1; - register u32 r1 asm("r1") = (u32)&context_id; - register u32 r2 asm("r2") = cmd_addr; + struct arm_smccc_res res; do { - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3", "r12"); - } while (r0 == QCOM_SCM_INTERRUPTED); - - return r0; + arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr, + 0, 0, 0, 0, 0, &res); + } while (res.a0 == QCOM_SCM_INTERRUPTED); + + return res.a0; } /** @@ -237,24 +226,12 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) { int context_id; + struct arm_smccc_res res; + + arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 1), + (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res); - register u32 r0 asm("r0") = SCM_LEGACY_ATOMIC_ID(svc, cmd, 1); - register u32 r1 asm("r1") = (u32)&context_id; - register u32 r2 asm("r2") = arg1; - - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3", "r12"); - return r0; + return res.a0; } /** @@ -270,26 +247,12 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) { int context_id; + struct arm_smccc_res res; + + arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 2), + (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res); - register u32 r0 asm("r0") = SCM_LEGACY_ATOMIC_ID(svc, cmd, 2); - register u32 r1 asm("r1") = (u32)&context_id; - register u32 r2 asm("r2") = arg1; - register u32 r3 asm("r3") = arg2; - - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") - __asmeq("%4", "r3") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2), "r" (r3) - : "r12"); - return r0; + return res.a0; } /**