Message ID | 1640856276-14697-2-git-send-email-quic_rajeevny@quicinc.com |
---|---|
State | New |
Headers | show |
Series | drm/msm/dsi: Add 10nm dsi phy tuning configuration support | expand |
On Thu, 30 Dec 2021 14:54:35 +0530, Rajeev Nandan wrote: > Add 10nm dsi phy tuning properties for phy drive strength and > phy drive level adjustemnt. > > Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> > --- > .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml: properties:phy-drive-strength-cfg:type: 'array' is not one of ['boolean', 'object'] from schema $id: http://devicetree.org/meta-schemas/core.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml: properties:phy-drive-level-cfg:type: 'array' is not one of ['boolean', 'object'] from schema $id: http://devicetree.org/meta-schemas/core.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml: ignoring, error in schema: properties: phy-drive-strength-cfg: type Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.example.dt.yaml:0:0: /example-0/dsi-phy@ae94400: failed to match any schema with compatible: ['qcom,dsi-phy-10nm'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1574124 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Quoting Rajeev Nandan (2021-12-30 01:24:35) > Add 10nm dsi phy tuning properties for phy drive strength and > phy drive level adjustemnt. s/adjustemnt/adjustment/ Please add the details about parasitics and eye shape tuning to this commit text. > > Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> > --- > .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > index 4399715..9406982 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > @@ -35,6 +35,18 @@ properties: > Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and > connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target > > + phy-drive-strength-cfg: > + type: array > + description: > + Register values of DSIPHY_RESCODE_OFFSET_TOP and DSIPHY_RESCODE_OFFSET_BOT > + for all five lanes to adjust the phy drive strength. > + > + phy-drive-level-cfg: > + type: array > + description: > + Register values of DSIPHY_RESCODE_OFFSET_TOP for all five lanes to adjust > + phy drive level/amplitude. It would be better to put human understandable values into DT here. This looks like a black box to anyone outside of qcom, so they won't know how to tune or set these register values. At least for phy-drive-level-cfg it sounds like it could be some sort of property that is a u32 array of 5 elements for each lane indicating some sort of amplitude, i.e. phy-max-amplitudes = <0 1 2 3 4>; phy-min-amplitudes = <0 1 2 3 4>; where each index corresponds to a particular lane. Then the driver can parse the amplitude and convert it into some sort of register value.
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml index 4399715..9406982 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -35,6 +35,18 @@ properties: Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target + phy-drive-strength-cfg: + type: array + description: + Register values of DSIPHY_RESCODE_OFFSET_TOP and DSIPHY_RESCODE_OFFSET_BOT + for all five lanes to adjust the phy drive strength. + + phy-drive-level-cfg: + type: array + description: + Register values of DSIPHY_RESCODE_OFFSET_TOP for all five lanes to adjust + phy drive level/amplitude. + required: - compatible - reg @@ -64,5 +76,12 @@ examples: clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; + + phy-drive-strength-cfg = [00 00 + 00 00 + 00 00 + 00 00 + 00 00]; + phy-drive-level-cfg = [59 59 59 59 59]; }; ...
Add 10nm dsi phy tuning properties for phy drive strength and phy drive level adjustemnt. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> --- .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)