| Message ID | 1643573719-32095-2-git-send-email-quic_rajeevny@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 3bcf3d8341080a7f79d8566aeadbd3c911391cfe |
| Headers | show |
| Series | [v5,1/3] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties | expand |
On Mon, 31 Jan 2022 01:45:17 +0530, Rajeev Nandan wrote: > In most cases, the default values of DSI PHY tuning registers should be > sufficient as they are fully optimized. However, in some cases where > extreme board parasitics cause the eye shape to degrade, the override > bits can be used to improve the signal quality. > > The general guidelines for DSI PHY tuning include: > - High and moderate data rates may benefit from the drive strength and > drive level tuning. > - Drive strength tuning will affect the output impedance and may be used > for matching optimization. > - Drive level tuning will affect the output levels without affecting the > impedance. > > The clock and data lanes have a calibration circuitry feature. The drive > strength tuning can be done by adjusting rescode offset for hstop/hsbot, > and the drive level tuning can be done by adjusting the LDO output level > for the HSTX drive. > > Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> > --- > > Changes in v2: > - More details in the commit text (Stephen Boyd) > - Use human understandable values (Stephen Boyd, Dmitry Baryshkov) > - Do not take values that are going to be unused (Dmitry Baryshkov) > > Changes in v3: > - Use "qcom," prefix (Dmitry Baryshkov) > - Remove encoding from phy-drive-ldo-level (Dmitry Baryshkov) > - Use negative values instead of two's complement (Dmitry, Rob Herring) > > Changes in v4: > - Fix dt_binding_check error (Rob Herring's bot) > > Changes in v5: > - None > > .../bindings/display/msm/dsi-phy-10nm.yaml | 36 ++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml index 4399715..2d5a766 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -35,6 +35,38 @@ properties: Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target + qcom,phy-rescode-offset-top: + $ref: /schemas/types.yaml#/definitions/int8-array + minItems: 5 + maxItems: 5 + description: + Integer array of offset for pull-up legs rescode for all five lanes. + To offset the drive strength from the calibrated value in an increasing + manner, -32 is the weakest and +31 is the strongest. + items: + minimum: -32 + maximum: 31 + + qcom,phy-rescode-offset-bot: + $ref: /schemas/types.yaml#/definitions/int8-array + minItems: 5 + maxItems: 5 + description: + Integer array of offset for pull-down legs rescode for all five lanes. + To offset the drive strength from the calibrated value in a decreasing + manner, -32 is the weakest and +31 is the strongest. + items: + minimum: -32 + maximum: 31 + + qcom,phy-drive-ldo-level: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: + The PHY LDO has an amplitude tuning feature to adjust the LDO output + for the HSTX drive. Use supported levels (mV) to offset the drive level + from the default value. + enum: [ 375, 400, 425, 450, 475, 500 ] + required: - compatible - reg @@ -64,5 +96,9 @@ examples: clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; + + qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>; + qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>; + qcom,phy-drive-ldo-level = <400>; }; ...
In most cases, the default values of DSI PHY tuning registers should be sufficient as they are fully optimized. However, in some cases where extreme board parasitics cause the eye shape to degrade, the override bits can be used to improve the signal quality. The general guidelines for DSI PHY tuning include: - High and moderate data rates may benefit from the drive strength and drive level tuning. - Drive strength tuning will affect the output impedance and may be used for matching optimization. - Drive level tuning will affect the output levels without affecting the impedance. The clock and data lanes have a calibration circuitry feature. The drive strength tuning can be done by adjusting rescode offset for hstop/hsbot, and the drive level tuning can be done by adjusting the LDO output level for the HSTX drive. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> --- Changes in v2: - More details in the commit text (Stephen Boyd) - Use human understandable values (Stephen Boyd, Dmitry Baryshkov) - Do not take values that are going to be unused (Dmitry Baryshkov) Changes in v3: - Use "qcom," prefix (Dmitry Baryshkov) - Remove encoding from phy-drive-ldo-level (Dmitry Baryshkov) - Use negative values instead of two's complement (Dmitry, Rob Herring) Changes in v4: - Fix dt_binding_check error (Rob Herring's bot) Changes in v5: - None .../bindings/display/msm/dsi-phy-10nm.yaml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+)