From patchwork Mon Feb 14 06:54:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 542576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70BE8C433FE for ; Mon, 14 Feb 2022 06:54:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230337AbiBNGyo (ORCPT ); Mon, 14 Feb 2022 01:54:44 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:49672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237307AbiBNGyn (ORCPT ); Mon, 14 Feb 2022 01:54:43 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 998DB575C5; Sun, 13 Feb 2022 22:54:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644821676; x=1676357676; h=from:to:cc:subject:date:message-id; bh=fMeakxJfvIFXrpp7I77SKHM3vjQmBLuSF3EbkTZcV6w=; b=ycZqzgouYnMT/uvO92/4S0UUQBp3fvu6I/FPzkGJ+jQAymvZuhjFptWb 0z+LuAIP9LjzMXqmyThkRRIIECG1FQdOL0aoJmmFzuxpHb4e1hX8Ybq2X c16mYhMX85y+CtpKAA4yW58krDuDenplEDvIGnkzNS/DT1U94KL0HS2R0 o=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 13 Feb 2022 22:54:35 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 Feb 2022 22:54:33 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 14 Feb 2022 12:24:31 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id BE1D84470; Mon, 14 Feb 2022 12:24:30 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rohit Agarwal Subject: [PATCH 1/8] dt-bindings: mailbox: Add binding for SDX65 APCS Date: Mon, 14 Feb 2022 12:24:28 +0530 Message-Id: <1644821668-18073-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree YAML binding for SDX65 APCS GCC block. The APCS block acts as the mailbox controller and also provides a clock output and takes 3 clock sources (pll, aux, ref) as input. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 01e9d91..688ae8b 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -91,6 +91,7 @@ allOf: compatible: enum: - qcom,sdx55-apcs-gcc + - qcom,sdx65-apcs-gcc then: properties: clocks: