From patchwork Mon Jun 27 10:44:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 585627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7598C43334 for ; Mon, 27 Jun 2022 10:44:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233627AbiF0Koq (ORCPT ); Mon, 27 Jun 2022 06:44:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232895AbiF0Kop (ORCPT ); Mon, 27 Jun 2022 06:44:45 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F3D563B2; Mon, 27 Jun 2022 03:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656326684; x=1687862684; h=from:to:cc:subject:date:message-id:mime-version; bh=lx+sq5BrYtlEATfMj2qSuWCQq/LYicVL0fuwLFTf85k=; b=qnM245RDku6rbAxyGynWMv2J6zFQ3WHGBzUTOMGzpmLtwndtoY7XFY50 Ye/+ISVGiDME7CZsY9FIfSCNf2ExkmYNaVfFKAEzXgqU9AVdBJVYDzTlH iJLS0IKZ9Q3SAlWlOOtwOCRbS6Zo0Mcp22xWnqz83YqCPdQfqwM6bctYJ I=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Jun 2022 03:44:44 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 03:44:43 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 03:44:42 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 03:44:37 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v2] ASoC: qcom: Add driver support for audioreach solution Date: Mon, 27 Jun 2022 16:14:22 +0530 Message-ID: <1656326662-14524-1-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Machine driver support for audioreach solution, which uses ADSP in SC7280 based paltforms. Signed-off-by: Srinivasa Rao Mandadapu --- Changes Since V1: -- Remove audioreach compatible name. -- Remove dt-binding patch. sound/soc/qcom/sc7280.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/sound/soc/qcom/sc7280.c b/sound/soc/qcom/sc7280.c index 34cdb99..da7469a 100644 --- a/sound/soc/qcom/sc7280.c +++ b/sound/soc/qcom/sc7280.c @@ -19,9 +19,11 @@ #include "../codecs/rt5682s.h" #include "common.h" #include "lpass.h" +#include "qdsp6/q6afe.h" #define DEFAULT_MCLK_RATE 19200000 #define RT5682_PLL_FREQ (48000 * 512) +#define MI2S_BCLK_RATE 1536000 struct sc7280_snd_data { struct snd_soc_card card; @@ -79,6 +81,7 @@ static int sc7280_headset_init(struct snd_soc_pcm_runtime *rtd) case MI2S_PRIMARY: case LPASS_CDC_DMA_RX0: case LPASS_CDC_DMA_TX3: + case TX_CODEC_DMA_TX_3: for_each_rtd_codec_dais(rtd, i, codec_dai) { rval = snd_soc_component_set_jack(component, &pdata->hs_jack, NULL); if (rval != 0 && rval != -ENOTSUPP) { @@ -164,10 +167,14 @@ static int sc7280_init(struct snd_soc_pcm_runtime *rtd) switch (cpu_dai->id) { case MI2S_PRIMARY: case LPASS_CDC_DMA_TX3: + case TX_CODEC_DMA_TX_3: return sc7280_headset_init(rtd); case LPASS_CDC_DMA_RX0: case LPASS_CDC_DMA_VA_TX0: case MI2S_SECONDARY: + case RX_CODEC_DMA_RX_0: + case SECONDARY_MI2S_RX: + case VA_CODEC_DMA_TX_0: return 0; case LPASS_DP_RX: return sc7280_hdmi_init(rtd); @@ -195,6 +202,10 @@ static int sc7280_snd_hw_params(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case LPASS_CDC_DMA_TX3: case LPASS_CDC_DMA_RX0: + case RX_CODEC_DMA_RX_0: + case SECONDARY_MI2S_RX: + case TX_CODEC_DMA_TX_3: + case VA_CODEC_DMA_TX_0: for_each_rtd_codec_dais(rtd, i, codec_dai) { sruntime = snd_soc_dai_get_stream(codec_dai, substream->stream); if (sruntime != ERR_PTR(-ENOTSUPP)) @@ -245,6 +256,9 @@ static int sc7280_snd_prepare(struct snd_pcm_substream *substream) switch (cpu_dai->id) { case LPASS_CDC_DMA_RX0: case LPASS_CDC_DMA_TX3: + case RX_CODEC_DMA_RX_0: + case TX_CODEC_DMA_TX_3: + case VA_CODEC_DMA_TX_0: return sc7280_snd_swr_prepare(substream); default: break; @@ -263,6 +277,9 @@ static int sc7280_snd_hw_free(struct snd_pcm_substream *substream) switch (cpu_dai->id) { case LPASS_CDC_DMA_RX0: case LPASS_CDC_DMA_TX3: + case RX_CODEC_DMA_RX_0: + case TX_CODEC_DMA_TX_3: + case VA_CODEC_DMA_TX_0: if (sruntime && data->stream_prepared[cpu_dai->id]) { sdw_disable_stream(sruntime); sdw_deprepare_stream(sruntime); @@ -291,6 +308,10 @@ static void sc7280_snd_shutdown(struct snd_pcm_substream *substream) SNDRV_PCM_STREAM_PLAYBACK); } break; + case SECONDARY_MI2S_RX: + snd_soc_dai_set_sysclk(cpu_dai, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, + 0, SNDRV_PCM_STREAM_PLAYBACK); + break; default: break; } @@ -298,14 +319,26 @@ static void sc7280_snd_shutdown(struct snd_pcm_substream *substream) static int sc7280_snd_startup(struct snd_pcm_substream *substream) { + unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS; + unsigned int codec_dai_fmt = SND_SOC_DAIFMT_CBS_CFS; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); int ret = 0; switch (cpu_dai->id) { case MI2S_PRIMARY: ret = sc7280_rt5682_init(rtd); break; + case SECONDARY_MI2S_RX: + codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S; + + snd_soc_dai_set_sysclk(cpu_dai, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, + MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK); + + snd_soc_dai_set_fmt(cpu_dai, fmt); + snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt); + break; default: break; }