From patchwork Fri Sep 23 13:05:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 608640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D25C6FA82 for ; Fri, 23 Sep 2022 13:07:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232326AbiIWNHn (ORCPT ); Fri, 23 Sep 2022 09:07:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232040AbiIWNHX (ORCPT ); Fri, 23 Sep 2022 09:07:23 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D03C13AF2C; Fri, 23 Sep 2022 06:07:22 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28NB6nwP024859; Fri, 23 Sep 2022 13:06:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=GydqGb27+64RCFiRn5sh0uPuMhU2BApFJTl+xlbCWOM=; b=X8FqxCa/jjX//YgR+Jud6OI+OJA+ZPqrkgsF/Nms7eo8k0wuQMPeM1wQOcIbVH4MjUiu eYhGmUWOjraHF2Rj2UfkCKYbtM0tcrLEoZ8nfXpgN3niJPam9KV3IX6zggziSFlzK13F 68CdCe3w4sZSGVg0Tz97yjjG/OzVKQAnXHyrSGWAPgtAliptz2BigbUVhULXWEtakRIq nS5mFkGWVtjBevvIi8PhOpT/D5szBfzOnJU7hBmK4oAbB/d3ZLUTKmI/p7o5vCzvtegz 9M0zv+VZ2LaBdzjfekEPapA3Hh/w3YNvmIMTa0jAlNM4rKgy6wAhwpS/i+QcPWIJ5uvA iQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jsbmxrg5s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Sep 2022 13:06:41 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28ND6e16018478 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Sep 2022 13:06:40 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 23 Sep 2022 06:06:35 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v8 7/7] remoteproc: qcom: Add support for memory sandbox Date: Fri, 23 Sep 2022 18:35:40 +0530 Message-ID: <1663938340-24345-8-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663938340-24345-1-git-send-email-quic_srivasam@quicinc.com> References: <1663938340-24345-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZeHd-5lPbccMqPHsi-KEwZ2cnqmRZp6N X-Proofpoint-ORIG-GUID: ZeHd-5lPbccMqPHsi-KEwZ2cnqmRZp6N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-23_04,2022-09-22_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209230085 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update pil driver with SMMU mapping for allowing authorised memory access to ADSP firmware, by carveout reserved adsp memory region from device tree file. Signed-off-by: Srinivasa Rao Mandadapu --- Changes since V6: -- Update smmu map and unmap function names. -- Revert adsp_ops const change. -- Move iommu check to within smmu map/unmap functions. Changes since V5: -- Remove adsp_rproc_unmap_smmu, adsp_of_unmap_smmu, adsp_of_map_smmu and adsp_rproc_map_smmu functions. -- Remove find_loaded_rsc_table call back initialization. -- Rename adsp_sandbox_needed to has_iommu. Changes since V4: -- Split the code and add appropriate APIs for resource allocation and free. -- Update adsp_unmap_smmu with missing free ops call. -- Update normalizing length value in adsp_of_unmap_smmu. Changes since V3: -- Rename is_adsp_sb_needed to adsp_sandbox_needed. -- Add smmu unmapping in error case and in adsp stop. Changes since V2: -- Replace platform_bus_type with adsp->dev->bus. -- Use API of_parse_phandle_with_args() instead of of_parse_phandle_with_fixed_args(). -- Replace adsp->is_wpss with adsp->is_adsp. -- Update error handling in adsp_start(). drivers/remoteproc/qcom_q6v5_adsp.c | 56 ++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index e463fbc..d89f3fa 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -48,6 +49,8 @@ #define LPASS_PWR_ON_REG 0x10 #define LPASS_HALTREQ_REG 0x0 +#define SID_MASK_DEFAULT 0xF + #define QDSP6SS_XO_CBCR 0x38 #define QDSP6SS_CORE_CBCR 0x20 #define QDSP6SS_SLEEP_CBCR 0x3c @@ -333,6 +336,47 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) return 0; } +static void adsp_unmap_carveout(struct rproc *rproc) +{ + struct qcom_adsp *adsp = rproc->priv; + + if (adsp->has_iommu) + iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size); +} + +static int adsp_map_carveout(struct rproc *rproc) +{ + struct qcom_adsp *adsp = rproc->priv; + struct of_phandle_args args; + long long sid; + unsigned long iova; + int ret; + + if (!adsp->has_iommu) + return 0; + + if (!rproc->domain) + return -EINVAL; + + ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args); + if (ret < 0) + return ret; + + sid = args.args[0] & SID_MASK_DEFAULT; + + /* Add SID configuration for ADSP Firmware to SMMU */ + iova = adsp->mem_phys | (sid << 32); + + ret = iommu_map(rproc->domain, iova, adsp->mem_phys, + adsp->mem_size, IOMMU_READ | IOMMU_WRITE); + if (ret) { + dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n"); + return ret; + } + + return 0; +} + static int adsp_start(struct rproc *rproc) { struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; @@ -343,9 +387,15 @@ static int adsp_start(struct rproc *rproc) if (ret) return ret; + ret = adsp_map_carveout(rproc); + if (ret) { + dev_err(adsp->dev, "ADSP smmu mapping failed\n"); + goto disable_irqs; + } + ret = clk_prepare_enable(adsp->xo); if (ret) - goto disable_irqs; + goto adsp_smmu_unmap; ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); @@ -401,6 +451,8 @@ static int adsp_start(struct rproc *rproc) qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); disable_xo_clk: clk_disable_unprepare(adsp->xo); +adsp_smmu_unmap: + adsp_unmap_carveout(rproc); disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); @@ -429,6 +481,8 @@ static int adsp_stop(struct rproc *rproc) if (ret) dev_err(adsp->dev, "failed to shutdown: %d\n", ret); + adsp_unmap_carveout(rproc); + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_adsp_pil_handover(&adsp->q6v5);