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[209.132.180.67]) by mx.google.com with ESMTP id f16si6192480pli.56.2017.01.11.07.59.16; Wed, 11 Jan 2017 07:59:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030548AbdAKP7P (ORCPT + 9 others); Wed, 11 Jan 2017 10:59:15 -0500 Received: from mail-wj0-f180.google.com ([209.85.210.180]:36360 "EHLO mail-wj0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030550AbdAKP7O (ORCPT ); Wed, 11 Jan 2017 10:59:14 -0500 Received: by mail-wj0-f180.google.com with SMTP id ew7so92159851wjc.3 for ; Wed, 11 Jan 2017 07:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=9ABtI858SDZuGbBGrH3AXXw0grkOlKSe+qFELJO24zg=; b=I2368Svh2LHIDYicI4+kjv2qNme+YPi3AHjGLAbJ82MxbGoEsoOYqk2ePNYr+oX7Eg zDDqbo5JFtJep4uQRsCeY8xvaewbD6kG8dqCw2l5h3ahNpo1qJ+4fhAofq4RSgCYf0tC wszaLsV35zOfARtztUZexQHEGDfnhkMx7bWnY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=9ABtI858SDZuGbBGrH3AXXw0grkOlKSe+qFELJO24zg=; b=H9IAz5D74U/Ff545d8TPO/Jo9XJ0BbKtkbAN7uyHpRdpShDGzaQtihF0l+8vTckY6s Ovp7/VrseJwvFcIENXfqeaVVPGwVoT7iSrPW31C3dkkd4N6I39z2KtXkRDn3e9Ps5ZXe KESVEvv20un4kx5nA8IZEXAcbUhnbwZdMY/UupBR8NSQMYYgyPw3YUcS9jOpLHv5bfeN Ih4/eDCgJrCApfipFEmdGocNtDY+rtpC/41EmLAK+lIUFMsmH3Zz6r4hyMlkqwYS4Iar I3cyCZlF4BFS9+v/FaXb0yUcfGLb6IyVWx9d5YQ9ghV3W3RfxIzjr62DoksYdBOylvuA 9+ag== X-Gm-Message-State: AIkVDXJ8GYpgmcswjtpHDOMVwPYIuqET4W4/lOPPFBWXS5tAZI9Eq3ogXtW7B0FqJlh6iIU5 X-Received: by 10.194.67.67 with SMTP id l3mr6378175wjt.151.1484150352590; Wed, 11 Jan 2017 07:59:12 -0800 (PST) Received: from mms-0441.wifi.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 14sm9732373wmk.1.2017.01.11.07.59.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Jan 2017 07:59:11 -0800 (PST) From: Georgi Djakov To: andy.gross@linaro.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, mathieu.poirier@linaro.org, zhang.chunyan@linaro.org, iivanov.xz@gmail.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, georgi.djakov@linaro.org Subject: [RESEND PATCH v5] arm64: dts: qcom: Add msm8916 CoreSight components Date: Wed, 11 Jan 2017 17:59:11 +0200 Message-Id: <20170111155911.29216-1-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: "Ivan T. Ivanov" Add initial set of CoreSight components found on Qualcomm msm8916 and apq8016 based platforms, including the DragonBoard 410c board. Signed-off-by: Ivan T. Ivanov Acked-by: Mathieu Poirier Signed-off-by: Georgi Djakov --- Changes since v4: (https://lkml.org/lkml/2016/11/17/533) * Move everything into the SoC dtsi file as suggested by Stephen Boyd. * Updated commit message. * Got Ack from Mathieu. Changes since v3: (https://lkml.org/lkml/2015/5/11/134) * Include msm8916-coresight.dtsi into msm8916.dtsi Changes since v2: (https://lkml.org/lkml/2015/4/29/242) * Added "1x" to "qcom,coresight-replicator" compatible string, to match what devicetree bindings documentations says. arch/arm64/boot/dts/qcom/msm8916.dtsi | 241 ++++++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index f8ff327667c5..014d76e7dddf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. MSM8916"; @@ -856,6 +857,246 @@ memory-region = <&mpss_mem>; }; }; + + tpiu@820000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x820000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + port { + tpiu_in: endpoint { + slave-mode; + remote-endpoint = <&replicator_out1>; + }; + }; + }; + + funnel@821000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x821000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - connected to Resource and Power Manger CPU ETM + * 1 - not-connected + * 2 - connected to Modem CPU ETM + * 3 - not-connected + * 5 - not-connected + * 6 - connected trought funnel to Wireless CPU ETM + * 7 - connected to STM component + */ + + port@4 { + reg = <4>; + funnel0_in4: endpoint { + slave-mode; + remote-endpoint = <&funnel1_out>; + }; + }; + port@8 { + reg = <0>; + funnel0_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + }; + + replicator@824000 { + compatible = "qcom,coresight-replicator1x", "arm,primecell"; + reg = <0x824000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + port@2 { + reg = <0>; + replicator_in: endpoint { + slave-mode; + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@825000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x825000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_out: endpoint { + slave-mode; + remote-endpoint = <&funnel0_out>; + }; + }; + port@1 { + reg = <0>; + etf_in: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etr@826000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x826000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + port { + etr_in: endpoint { + slave-mode; + remote-endpoint = <&replicator_out0>; + }; + }; + }; + + funnel@841000 { /* APSS funnel only 4 inputs are used */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x841000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + funnel1_in1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + funnel1_in2: endpoint { + slave-mode; + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + funnel1_in3: endpoint { + slave-mode; + remote-endpoint = <&etm3_out>; + }; + }; + port@4 { + reg = <0>; + funnel1_out: endpoint { + remote-endpoint = <&funnel0_in4>; + }; + }; + }; + }; + + etm@85c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85c000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + port { + etm0_out: endpoint { + remote-endpoint = <&funnel1_in0>; + }; + }; + }; + + etm@85d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85d000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + port { + etm1_out: endpoint { + remote-endpoint = <&funnel1_in1>; + }; + }; + }; + + etm@85e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85e000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + port { + etm2_out: endpoint { + remote-endpoint = <&funnel1_in2>; + }; + }; + }; + + etm@85f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85f000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + port { + etm3_out: endpoint { + remote-endpoint = <&funnel1_in3>; + }; + }; + }; }; smd {