From patchwork Tue Dec 5 15:46:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120697 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5906008qgn; Tue, 5 Dec 2017 07:47:17 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ+sxSi58IOOt3Nwykc8TcyhNGzACTK6MSY1mdTtBmukVxYs25LcwpPLPhS/7BSR2eS5LsX X-Received: by 10.159.246.7 with SMTP id b7mr18118729pls.81.1512488837624; Tue, 05 Dec 2017 07:47:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512488837; cv=none; d=google.com; s=arc-20160816; b=GzwTRFoUel2/nHCgBdA/31GNXnrlbHE/KFCRhxVVACot/27BAly5WaCoLjTLgMCDFW 1rbBnABgOlLwLY/i1jq2vkYDSaahrLOT+ODdXwSn/KtJtOpCxAnCWeS19JcO+eDfDptt kaxTlRUWXbVtqECaHaoutn80yGnewj3DX3A4VXH+ppwSAPPevkWhHix5jGCS5KK6I2/Y peHVjDpYDFssKjzkM0r6PAUkp0un8FiHzqyDOFbgXvSnnQwOcJkdGSuT0/2e7AAJwlEG 1Fo7sMS2mz3oY9tzwDZuVtazT8CRgQC8sJx5nU6FI3IF7TMYbL5PnLMFKjkGhFvwLfuX gqbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lZKWFcv8Ah/nvCcZNe5Xgnr0L8SB44b62DaUCit33rA=; b=Zx5Eg0v834yYutLpCrpUAm2ZP1yGcKxM9+4I2h4B0ukLhIfcw2H7Up764xx4c4lxWe q0tCQARagBFwSokUG8wHMYZlVa0y5Stwa0S9xFx1xgbrghLSScROfOiLpqyqcC8cyecH 9ZjnCG7egYa0TlBWlPr7EUkfQhHD4wc6IvfeOI5513D/Ikfs+jFGzbGvowDRKogGAdqk IDH4G8eeE0JOgXgM+KA83iFnOY5SnCEXm39RTTViN/5dkbya+xy59UNSO4T0LpoHD3i0 fPdPvUbx5JrD1I+QdD4qvPaaV3iCXlTRhajM4HNm5YbsQmFaeXAvRJtGT47PNNl7JsGy KhIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Obpm+9Bw; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j23si238495pll.748.2017.12.05.07.47.17; Tue, 05 Dec 2017 07:47:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Obpm+9Bw; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752977AbdLEPrP (ORCPT + 10 others); Tue, 5 Dec 2017 10:47:15 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:40707 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753050AbdLEPrJ (ORCPT ); Tue, 5 Dec 2017 10:47:09 -0500 Received: by mail-wm0-f65.google.com with SMTP id f206so2067140wmf.5 for ; Tue, 05 Dec 2017 07:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SAMVO+dOf8LdSV5eqwOijQZV7TffAdH+tZur48Tw+Q8=; b=Obpm+9BwPYa/Pm/2I9KF+eovPG9Aw4ZuXcJKrJ6CXBKT/8iIDLbBWaZHWVc7aFB4gs 1w28iZKg+fjd3A0lONbjIVP4fBZGtH8HIY9T9mBuyk0HOFURlBJ6yEer1Nj6d8As0v/K xKjLRonP5GhGgmqIvrZxSkq+KVARZVRJ6lk34= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SAMVO+dOf8LdSV5eqwOijQZV7TffAdH+tZur48Tw+Q8=; b=GGzcYdeZ6H2L7btqJRzfxskoifxd+hs3FIsR6g+6Wf0SoEK6iLC5ex+WSg9+bJwF/t IYtmflyHkuuaxUH73RvO3qzHdhgQ5PDrZngbPe/X7LEMENl3QwTZeT+BfsrdGAqVgkOb 0iROb9srXEQ9Y4erGQ0zSsul6y43wCRhX0nC1iE27VZE82QownRkAeCwEA6IBYz3+MOu SEyeQMKKiBJzBLzS4JON4H76lvO4zhzV3TYSRQj/nR2SY+PAOWUWVND9lLg+FN1P7Xw7 XADp4HAHDs5Rw1CC8KN2XvztqN1t6wk6G3g7iGNKktaf7GT5bB3HSmUjsL0yxTF4kR6V EWWg== X-Gm-Message-State: AKGB3mJwT3XVK91xZa9bIvC/dEZqPFkw7uycZ8mdcHNsZXyEUwSNPzP5 D8drsE+FcH2BJiqp0yd464/Edw== X-Received: by 10.28.232.220 with SMTP id f89mr8563076wmi.57.1512488828320; Tue, 05 Dec 2017 07:47:08 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id v47sm500946wrc.13.2017.12.05.07.47.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Dec 2017 07:47:07 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org Cc: mturquette@baylibre.com, robh@kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v11 3/6] clk: qcom: Add A53 PLL support Date: Tue, 5 Dec 2017 17:46:58 +0200 Message-Id: <20171205154701.27730-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171205154701.27730-1-georgi.djakov@linaro.org> References: <20171205154701.27730-1-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++ drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 110 +++++++++++++++++++++ 4 files changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt new file mode 100644 index 000000000000..e3fa8118eaee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt @@ -0,0 +1,22 @@ +Qualcomm MSM8916 A53 PLL Binding +-------------------------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,msm8916-a53pll" + +- reg : shall contain base register location and length + +- #clock-cells : must be set to <0> + +Example: + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9f6c278deead..81ac7b9378fe 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -12,6 +12,16 @@ config COMMON_CLK_QCOM select REGMAP_MMIO select RESET_CONTROLLER +config QCOM_A53PLL + bool "MSM8916 A53 PLL" + depends on COMMON_CLK_QCOM + default ARCH_QCOM + help + Support for the A53 PLL on MSM8916 devices. It provides + the CPU with frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on MSM8916 + devices. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 26410d31446b..e767c60c24ec 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..c18cb7614e42 --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm A53 PLL driver + * + * Copyright (c) 2017, Linaro Limited + * Author: Georgi Djakov + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static const struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 63, 0x0, 0x1, 0 }, + { 1248000000, 65, 0x0, 0x1, 0 }, + { 1363200000, 71, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, +}; + +static int qcom_a53pll_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + return 0; +} + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct resource *res; + struct clk_pll *pll; + void __iomem *base; + struct clk_init_data init = { }; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04; + pll->m_reg = 0x08; + pll->n_reg = 0x0c; + pll->config_reg = 0x14; + pll->mode_reg = 0x00; + pll->status_reg = 0x1c; + pll->status_bit = 16; + pll->freq_tbl = a53pll_freq; + + init.name = "a53pll"; + init.parent_names = (const char *[]){ "xo" }; + init.num_parents = 1; + init.ops = &clk_pll_sr2_ops; + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + ret = devm_clk_register_regmap(dev, &pll->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,msm8916-a53pll" }, + { } +}; + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .remove = qcom_a53pll_remove, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver);