From patchwork Mon Dec 10 20:56:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 153354 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4002493ljp; Mon, 10 Dec 2018 12:56:28 -0800 (PST) X-Google-Smtp-Source: AFSGD/VsvkkUcMa4JlRPXI/9nUgGdyBpu4bpVAm6mFtBLWstRqEM6v29Jr6XNd28z/TI3DHmim5g X-Received: by 2002:a17:902:c5:: with SMTP id a63mr13708891pla.267.1544475388596; Mon, 10 Dec 2018 12:56:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544475388; cv=none; d=google.com; s=arc-20160816; b=Gs6iQX9WDsTz/GP8f517Y2sbtKOikbCokQYDaCzn52FVUijvFkg23WLDeVgyPTiuBe 9/qzTGcZCXdixIKQoQbmQtbC5hS/O7Jv8rkAbLPf/vFnhSKqNeRiZ9QYOYt+Xn7TTlgG yt0EaXqmh0IbfuQwd3t8JScEZFXMDFxLHx4Ygdwr7P1GbkN48UUrRzbcPWITa4FZeMiK 6u41mmcmhKQsDUlNKwT6QWavwEjQK2J03LNcaO9DrjhaIefSS9jkn551GhXyQOEUJDkp HFInkMBs87YkuKkljlNRX4UTRh8h/7vw01BuPIpxiikNcRKXGfcJDObjduTePP9ji2E4 kZBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=jDPsFe4rO0j+yrMvBmecpetuHS48166TMpNdIWeWCIM=; b=zYVqImkMn2wqS3pQNns2YHylJYApEf9Z3EIsotS0eA8ZNnFZIdkNFMQiUDVFtr4oQe /1Y2Q0XTq3pEQFpz8fPbZIUsKyAeEJy9BMc2gy+IjlxFh/9uGHS7WEcq8CdkXyEOJuoj 9VXWkcjKHXsJ+96NG9OgZv/jZsvnNd4ZAxsaPNV5vd4IOBrrjsG3G3QIS4V1rdbhL6eC Zu+6qd1VgDkiDCvqJub88wbEzYwLm/Ux4tITMlHS1r3XAxl0Ts4PKWVcniQTD5Na4MfW up1YTv3TnR9fDr/tlqjj1H/6PNKj87BtJJcUVonnhni7psDsEoxBbwc9WbXiIqZiXuvS eKCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w7si9688128ply.421.2018.12.10.12.56.27; Mon, 10 Dec 2018 12:56:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728820AbeLJU41 (ORCPT + 15 others); Mon, 10 Dec 2018 15:56:27 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:44849 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727538AbeLJU41 (ORCPT ); Mon, 10 Dec 2018 15:56:27 -0500 Received: from wuerfel.lan ([109.192.41.194]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.129]) with ESMTPA (Nemesis) id 1Mt7Ll-1hL8Pc3kbp-00tQGY; Mon, 10 Dec 2018 21:56:21 +0100 From: Arnd Bergmann To: Rob Clark , David Airlie Cc: Arnd Bergmann , Jonathan Marek , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/msm: fix arm64 build error Date: Mon, 10 Dec 2018 21:56:12 +0100 Message-Id: <20181210205620.3041207-1-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 MIME-Version: 1.0 X-Provags-ID: V03:K1:J5G1z7eID905HVHqXVHn+k7iZcCWvCQxXxcVFWADVapF9JmJu0Q hTFQic1eb7oTgOBPqPKx3jT4xOfeo3B2Nc4acyxNjion7hkmIgm0SmgreNdm5WFi9uSOTSD b1lpMjKTgB7y9MhiuX3QFi5UkCfzV/WIHVhJrzRpE4eqZJMADzah/ypgPtDCmNqMZtqUuHe fmSM48uqo5dPe1O/TsQcA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:9IiwERIOtWE=:i3+Ucu6/BKdx070CCC+zI8 pyb5+fVQrKl/NNm6bQmVUOa8fFccQpFGSpgbycNoS1F+NqUI883DDHqXW4nBqfAB9yuQ4ItmQ JpnZ50wbjXRO7KGLasDi+jLtcL4kitCnWTouqJonH2ymSuHaunIXgs2lMyDT4uVHaDVlqG6iv nXKLPgnTKDmMD2DEOxQjR0Qcc37cFjjTYpn01RBhgtVZEzlXm+PuC+zYGA9PsC2qXnGxTIKaF 3mt+dveT2jiRnGfeCY9WN+d2WigX51oK07mzkfZDiW3voSjg1jFDu1EgroOJv5bnijFKXpUJP lWfjad8eGUPzVIur9MBQHsEVDpPCPPue+bi/DEBSmvbI8LaILkYKfzZfvEQsUV+bl6V+Fwt2f 9uKEYNx0KqiIsGMV+4KjfKXtGIFn8u15/2EnL4OHwRGKMjHURhRtF0FHiz2oD0c5jrE/GfkPb vem9D6dZohciYlN4dQQSB6a+Cacr0kxbLj3MX/mdH7MmAlxkYW8Wlm0ySJQUKgoxUMgTLr/kc rVf1315zgBrBBiTSYQnm1/owBTPKDH3Uh+GSeKJPgVknTWfiaK9BLO79HqlFIUsAKnLXdn0cM pibg1Ciwigk0RL9X9EEFtNVU+A2YQeor+NC9qb+MM5vRrQm5r5fS9VTSeumoDlzQAT+Cc7uRh kKU1MGVSQCtKJosU4n+jYlXotARkRUnbCKsllGJXDf0pHa77XE3amQJLqsihBPa1o1GEwHa+5 RqcOgrkS9aa6i2Y8x7QuCWhp4GKXE5dEpn52+g== Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The new a200 GPU MMU support fails to build on arm64 because of a conflicting macro name: drivers/gpu/drm/msm/msm_gpummu.c:17: error: "VA_START" redefined [-Werror] #define VA_START SZ_16M In file included from arch/arm64/include/asm/pgtable-hwdef.h:19, from arch/arm64/include/asm/processor.h:48, from include/linux/mutex.h:19, from include/linux/notifier.h:14, from include/linux/clk.h:17, from drivers/gpu/drm/msm/msm_drv.h:23, from drivers/gpu/drm/msm/msm_gpummu.c:4: arch/arm64/include/asm/memory.h:51: note: this is the location of the previous definition #define VA_START (UL(0xffffffffffffffff) - \ Rename this and the related macros with a GPU_ prefix. Fixes: 1c0088f255ae ("drm/msm: implement a2xx mmu") Signed-off-by: Arnd Bergmann --- drivers/gpu/drm/msm/msm_gpummu.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) -- 2.20.0 diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/msm_gpummu.c index f1dc2b7e5fd3..2a7ddd449d3d 100644 --- a/drivers/gpu/drm/msm/msm_gpummu.c +++ b/drivers/gpu/drm/msm/msm_gpummu.c @@ -14,10 +14,10 @@ struct msm_gpummu { }; #define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base) -#define VA_START SZ_16M -#define VA_RANGE (0xfff * SZ_64K) -#define MMU_PAGE_SIZE SZ_4K -#define TABLE_SIZE (sizeof(uint32_t) * VA_RANGE / MMU_PAGE_SIZE) +#define GPU_VA_START SZ_16M +#define GPU_VA_RANGE (0xfff * SZ_64K) +#define GPU_MMU_PAGE_SIZE SZ_4K +#define GPU_TABLE_SIZE (sizeof(uint32_t) * GPU_VA_RANGE / GPU_MMU_PAGE_SIZE) static int msm_gpummu_attach(struct msm_mmu *mmu, const char * const *names, int cnt) @@ -34,7 +34,7 @@ static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, unsigned len, int prot) { struct msm_gpummu *gpummu = to_msm_gpummu(mmu); - unsigned idx = (iova - VA_START) / MMU_PAGE_SIZE; + unsigned idx = (iova - GPU_VA_START) / GPU_MMU_PAGE_SIZE; struct scatterlist *sg; unsigned prot_bits = 0; unsigned i, j; @@ -46,9 +46,9 @@ static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova, for_each_sg(sgt->sgl, sg, sgt->nents, i) { dma_addr_t addr = sg->dma_address; - for (j = 0; j < sg->length / MMU_PAGE_SIZE; j++, idx++) { + for (j = 0; j < sg->length / GPU_MMU_PAGE_SIZE; j++, idx++) { gpummu->table[idx] = addr | prot_bits; - addr += MMU_PAGE_SIZE; + addr += GPU_MMU_PAGE_SIZE; } } @@ -62,10 +62,10 @@ static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova, static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, unsigned len) { struct msm_gpummu *gpummu = to_msm_gpummu(mmu); - unsigned idx = (iova - VA_START) / MMU_PAGE_SIZE; + unsigned idx = (iova - GPU_VA_START) / GPU_MMU_PAGE_SIZE; unsigned i; - for (i = 0; i < len / MMU_PAGE_SIZE; i++, idx++) + for (i = 0; i < len / GPU_MMU_PAGE_SIZE; i++, idx++) gpummu->table[idx] = 0; gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, @@ -78,7 +78,7 @@ static void msm_gpummu_destroy(struct msm_mmu *mmu) { struct msm_gpummu *gpummu = to_msm_gpummu(mmu); - dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base, + dma_free_attrs(mmu->dev, GPU_TABLE_SIZE, gpummu->table, gpummu->pt_base, DMA_ATTR_FORCE_CONTIGUOUS); kfree(gpummu); @@ -100,7 +100,7 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) if (!gpummu) return ERR_PTR(-ENOMEM); - gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base, + gpummu->table = dma_alloc_attrs(dev, GPU_TABLE_SIZE + 32, &gpummu->pt_base, GFP_KERNEL | __GFP_ZERO, DMA_ATTR_FORCE_CONTIGUOUS); if (!gpummu->table) { kfree(gpummu); @@ -119,5 +119,5 @@ void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, dma_addr_t base = to_msm_gpummu(mmu)->pt_base; *pt_base = base; - *tran_error = base + TABLE_SIZE; /* 32-byte aligned */ + *tran_error = base + GPU_TABLE_SIZE; /* 32-byte aligned */ }