From patchwork Mon Feb 11 07:39:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 157969 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2302670jaa; Sun, 10 Feb 2019 23:40:15 -0800 (PST) X-Google-Smtp-Source: AHgI3IbqB+ifAORjq+SJlDNmRnoVBVBraUyqnmR+Dc+rqhInXFwTkVkT+TFI15bI4jsX/7Mfbb1O X-Received: by 2002:a63:4d:: with SMTP id 74mr32810369pga.248.1549870814981; Sun, 10 Feb 2019 23:40:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549870814; cv=none; d=google.com; s=arc-20160816; b=Gp0Csy6Xs0Hc8wQyBzDpUg4bFfaGEueodnOWQrik+AeYup9Ng6PaRMh718cRaGlJSC mRCo7f3TT2HIRcPbC/rPPBYhRHXkb/wPBKQY+ELghGURFnsRm8O+0AMOpgRqKGuEjY8v tCaqfOewgWCTDYfMkfW4vfzBr8Uw/HCNShXsAPzyZzMs02KomJy/ys33ZaQqmsLi81Sg NqzwHg0FLjuPTlmh+EACeGROcMGfA7cIDXgLeiOp8OnMpmvnPKkwuGNikB36fDVM8sB6 2K1jyMrhOXR8M4bW0ylTEr3Wl9Q92cqFvomLAKLEcwS+1Z+hov1+W350dZH/YGj/l8dP niYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XbHtz9Y94aj6aVYJIKMZ7QW3PvjkEZpJZyM9ZGK0qQY=; b=Bb9hXwWecwZbyq02bWT9EPAA4uqyHAIifmstZ0ESEHnLkGyx9qcqTiJygRkb9CNgyb DWJ/vcYoG9vZKjF7b5wHBWfBFij9CMYKTtlEuMFMDewZK3/Se3dkruIj4Asm0y+lbbNb mbzaZ+O5N8Mp3nc1M4WYL+GbBzS2Tz8LnDFcNu+0xYn48XvnqMLqulXZbBCVAL5HAy+s iUOk3H6O8I4S7tZOMmiKoutvqZAct6fcmtSMdejhXnAf3a5oXKfFSgoLD0YyZfx+r80j p15IH6olFv9ieth6C5Qs4Psgeche1UA/BYJHYMFhY6pnsQV/ii9SOwWsFjStCh2Qg8og DQmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=1l9skCXt; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b86si269925pfc.217.2019.02.10.23.40.14; Sun, 10 Feb 2019 23:40:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=1l9skCXt; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726819AbfBKHkO (ORCPT + 15 others); Mon, 11 Feb 2019 02:40:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:57374 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725931AbfBKHkO (ORCPT ); Mon, 11 Feb 2019 02:40:14 -0500 Received: from localhost.localdomain (unknown [117.99.91.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 67E2721479; Mon, 11 Feb 2019 07:40:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549870812; bh=Nzp/hm+HXwku9rUt5Yoyb+DN510RxldbZfrGiL9aqoY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1l9skCXtTXpNZSWE3Nfk4Uz0BbTuD0N3d1sm0mcrA51OpTOV626pMJivU+86t02iL 84ZHJUzveVhBabEgZ9L5sQOeclUnjKMk8l1pl+y7xYsKI87+Z03tNgLa4NdhkluJuk 1P16Ii2Aji+3XmXha1lcecFv3V2xdA7cZcDEu1NY= From: Vinod Koul To: Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Taniya Das , Andy Gross , David Brown , linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, Anu Ramanathan , Shawn Guo , Vinod Koul Subject: [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Date: Mon, 11 Feb 2019 13:09:27 +0530 Message-Id: <20190211073928.20456-2-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190211073928.20456-1-vkoul@kernel.org> References: <20190211073928.20456-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Taniya Das The RCG CFG/M/N/D register base could be at a different offset than the CMD register, so introduce a cfg_offset to identify the offset with respect to the CMD RCGR register. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan Signed-off-by: Shawn Guo Signed-off-by: Vinod Koul --- Changes in v2: - add macros and update comment drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 24 ++++++++++++++---------- 2 files changed, 16 insertions(+), 10 deletions(-) -- 2.20.1 diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 91336a030179..c25b57c3cbc8 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -138,6 +138,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table * @clkr: regmap clock handle + * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG */ struct clk_rcg2 { u32 cmd_rcgr; @@ -147,6 +148,7 @@ struct clk_rcg2 { const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; + u8 cfg_off; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6e3bd195d012..8c02bffe50df 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -41,6 +41,11 @@ #define N_REG 0xc #define D_REG 0x10 +#define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) +#define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) +#define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) +#define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) + /* Dynamic Frequency Scaling */ #define MAX_PERF_LEVEL 8 #define SE_CMD_DFSR_OFFSET 0x14 @@ -74,7 +79,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) u32 cfg; int i, ret; - ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); if (ret) goto err; @@ -123,7 +128,7 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) int ret; u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, + ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), CFG_SRC_SEL_MASK, cfg); if (ret) return ret; @@ -162,13 +167,13 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); if (rcg->mnd_width) { mask = BIT(rcg->mnd_width) - 1; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m); + regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); m &= mask; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n); + regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); n = ~n; n &= mask; n += m; @@ -263,17 +268,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (rcg->mnd_width && f->n) { mask = BIT(rcg->mnd_width) - 1; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + M_REG, mask, f->m); + RCG_M_OFFSET(rcg), mask, f->m); if (ret) return ret; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m)); + RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); if (ret) return ret; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + D_REG, mask, ~f->n); + RCG_D_OFFSET(rcg), mask, ~f->n); if (ret) return ret; } @@ -284,8 +289,7 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; - - return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, + return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), mask, cfg); }