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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z126sm17129194pfb.100.2019.06.11.21.45.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 21:45:41 -0700 (PDT) From: Bjorn Andersson Cc: Andy Gross , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 3/4] arm64: dts: qcom: Add AOSS QMP node Date: Tue, 11 Jun 2019 21:45:35 -0700 Message-Id: <20190612044536.13940-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190612044536.13940-1-bjorn.andersson@linaro.org> References: <20190612044536.13940-1-bjorn.andersson@linaro.org> To: unlisted-recipients:; (no To-header on input) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v8: - None arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c5a5c5b086b1..c80881309f79 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2448,6 +2448,16 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,