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[37.119.134.251]) by smtp.gmail.com with ESMTPSA id w20sm291013wmk.34.2019.12.05.08.15.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 05 Dec 2019 08:15:07 -0800 (PST) From: Paolo Pisati To: Andy Gross , Amit Pundir , Manu Gautam , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH 1/6] clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock Date: Thu, 5 Dec 2019 17:15:00 +0100 Message-Id: <20191205161505.15295-2-p.pisati@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191205161505.15295-1-p.pisati@gmail.com> References: <20191205161505.15295-1-p.pisati@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Amit Pundir Clock "gcc_aggre1_pnoc_ahb_clk" added in QcomLT commit 9a108d744fda ("clk: qcom: Add some missing gcc clks for msm8996"), broke USB gagdets for db820c. So drop it for now and re-visit the dropped changes while submitting it upstream. Fixes: 9a108d744fda ("clk: qcom: Add some missing gcc clks for msm8996") Signed-off-by: Amit Pundir --- drivers/clk/qcom/gcc-msm8996.c | 15 --------------- 1 file changed, 15 deletions(-) -- 2.7.4 diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index d004cda..c1e1148 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -2937,20 +2937,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { }, }; -static struct clk_branch gcc_aggre1_pnoc_ahb_clk = { - .halt_reg = 0x82014, - .clkr = { - .enable_reg = 0x82014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre1_pnoc_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_aggre2_ufs_axi_clk = { .halt_reg = 0x83014, .clkr = { @@ -3453,7 +3439,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = { [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr, [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr, [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr, - [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr, [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,