From patchwork Mon Apr 13 17:01:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 189625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CD6BC2BBFD for ; Mon, 13 Apr 2020 17:01:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B756206E9 for ; Mon, 13 Apr 2020 17:01:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="Kpa31S9W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732281AbgDMRBW (ORCPT ); Mon, 13 Apr 2020 13:01:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1732278AbgDMRBU (ORCPT ); Mon, 13 Apr 2020 13:01:20 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5ADEBC008749 for ; Mon, 13 Apr 2020 10:01:20 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id s8so10855738wrt.7 for ; Mon, 13 Apr 2020 10:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ifz7eEgQDkI/yAEt03RoeGqs19nYSssxU5j/gJ4Dim0=; b=Kpa31S9WV4DB2epJ0brmlqCYF1LhiH7z0L6PGh4Wbzcd03Fn0R+4GpBmxvFEB7UwNs tfXfQdPF8/Hp/4af5lAokIt68Wyxat3WatIWk7ZEitiTrGuHw2acegBAEv0i/7Hn0iuy ZSPISg9Pl1NZZW2DtFYy5nSyOoczsqC5qAUIGoV9LT7y7SwQGQZ5a4RcFT1bcdGDEYKv 7CH50QYVjnEq1z3Mvr4EV4bIV4wAY6Btp5ypPFZETulZ0qzAG6e0LAgVC6tKR3VCE58z Y9E0wIaZm1/uVvZIw3Nc8wtYDlya9c8AWTu7VRTCXRgJRDBptbDHNrPZtl608d5u+QJY 2vwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ifz7eEgQDkI/yAEt03RoeGqs19nYSssxU5j/gJ4Dim0=; b=NwV0KqPK6PhUDQkD6mTsCd4NXHXFn/s3xHwx2wzUAFdHow4cI1rulYpxDZAq2d6rEW XrEghg62/gZebhLtrgMESGhtHfGQRZ42MRy2QuBu1cdRwHcxJ1E7Rh5AX6Vdh+PPykjS ZNMKvzw1+zk2yyE0J5XwbJ2/wEF6BQ0jXXn2190zONuE2wdxXjoNnlPNbeh0Y1cZQnz3 RePK/fmLI0+h49evacav2fDNbbFSdZ8pCh4CeErD0OX6rfRcbnhQ7hX0+sD73mMU7kXA aWyZttN/zhwK4zQXUSxYI54HXOgMtTMsQ+9KYP2bpNlQt6CGFdgQfDpOOUtevsRDOTSo rNkg== X-Gm-Message-State: AGi0PuZGW+bbmrcA1x0/dzKt4Jz6PL7b1pDC6stjRt0XPHBSaOp+ge2H or9WaV2pKW6kMmU+BS6r4q+8Yg== X-Google-Smtp-Source: APiQypI5L7HxfafpOR4GRvpAW8MC8kqY/R8iWGtx4F0odEFkYwngaQANZQgPqx5hNnsILB/TjEYY0w== X-Received: by 2002:adf:e3ca:: with SMTP id k10mr2020584wrm.53.1586797278826; Mon, 13 Apr 2020 10:01:18 -0700 (PDT) Received: from localhost.localdomain ([2001:470:1f1b:192:29fe:7bf:41fe:904d]) by smtp.googlemail.com with ESMTPSA id q187sm15443268wma.41.2020.04.13.10.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2020 10:01:18 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko , Christian Lamparter , Luka Perkov Subject: [PATCH 1/3] net: phy: mdio: add IPQ40xx MDIO driver Date: Mon, 13 Apr 2020 19:01:05 +0200 Message-Id: <20200413170107.246509-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.0 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the driver for the MDIO interface inside of Qualcomm IPQ40xx series SoC-s. Signed-off-by: Christian Lamparter Signed-off-by: Robert Marko Cc: Luka Perkov --- drivers/net/phy/Kconfig | 7 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-ipq40xx.c | 180 +++++++++++++++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 drivers/net/phy/mdio-ipq40xx.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 9dabe03a668c..614d08635012 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -157,6 +157,13 @@ config MDIO_I2C This is library mode. +config MDIO_IPQ40XX + tristate "Qualcomm IPQ40xx MDIO interface" + depends on HAS_IOMEM && OF + help + This driver supports the MDIO interface found in Qualcomm + IPQ40xx series Soc-s. + config MDIO_MOXART tristate "MOXA ART MDIO interface support" depends on ARCH_MOXART || COMPILE_TEST diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fe5badf13b65..c89fc187fd74 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o +obj-$(CONFIG_MDIO_IPQ40XX) += mdio-ipq40xx.o obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o diff --git a/drivers/net/phy/mdio-ipq40xx.c b/drivers/net/phy/mdio-ipq40xx.c new file mode 100644 index 000000000000..8068f1e6a077 --- /dev/null +++ b/drivers/net/phy/mdio-ipq40xx.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MDIO_CTRL_0_REG 0x40 +#define MDIO_CTRL_1_REG 0x44 +#define MDIO_CTRL_2_REG 0x48 +#define MDIO_CTRL_3_REG 0x4c +#define MDIO_CTRL_4_REG 0x50 +#define MDIO_CTRL_4_ACCESS_BUSY BIT(16) +#define MDIO_CTRL_4_ACCESS_START BIT(8) +#define MDIO_CTRL_4_ACCESS_CODE_READ 0 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1 +#define CTRL_0_REG_DEFAULT_VALUE 0x150FF + +#define IPQ40XX_MDIO_RETRY 1000 +#define IPQ40XX_MDIO_DELAY 10 + +struct ipq40xx_mdio_data { + struct mii_bus *mii_bus; + void __iomem *membase; + struct device *dev; +}; + +static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am) +{ + int i; + + for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) { + unsigned int busy; + + busy = readl(am->membase + MDIO_CTRL_4_REG) & + MDIO_CTRL_4_ACCESS_BUSY; + if (!busy) + return 0; + + /* BUSY might take to be cleard by 15~20 times of loop */ + udelay(IPQ40XX_MDIO_DELAY); + } + + dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name); + + return -ETIMEDOUT; +} + +static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + struct ipq40xx_mdio_data *am = bus->priv; + int value = 0; + unsigned int cmd = 0; + + lockdep_assert_held(&bus->mdio_lock); + + if (ipq40xx_mdio_wait_busy(am)) + return -ETIMEDOUT; + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG); + + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ; + + /* issue read command */ + writel(cmd, am->membase + MDIO_CTRL_4_REG); + + /* Wait read complete */ + if (ipq40xx_mdio_wait_busy(am)) + return -ETIMEDOUT; + + /* Read data */ + value = readl(am->membase + MDIO_CTRL_3_REG); + + return value; +} + +static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 value) +{ + struct ipq40xx_mdio_data *am = bus->priv; + unsigned int cmd = 0; + + lockdep_assert_held(&bus->mdio_lock); + + if (ipq40xx_mdio_wait_busy(am)) + return -ETIMEDOUT; + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG); + + /* issue write data */ + writel(value, am->membase + MDIO_CTRL_2_REG); + + cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_WRITE; + /* issue write command */ + writel(cmd, am->membase + MDIO_CTRL_4_REG); + + /* Wait write complete */ + if (ipq40xx_mdio_wait_busy(am)) + return -ETIMEDOUT; + + return 0; +} + +static int ipq40xx_mdio_probe(struct platform_device *pdev) +{ + struct ipq40xx_mdio_data *am; + struct resource *res; + + am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL); + if (!am) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no iomem resource found\n"); + return -ENXIO; + } + + am->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(am->membase)) { + dev_err(&pdev->dev, "unable to ioremap registers\n"); + return PTR_ERR(am->membase); + } + + am->mii_bus = devm_mdiobus_alloc(&pdev->dev); + if (!am->mii_bus) + return -ENOMEM; + + writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG); + + am->mii_bus->name = "ipq40xx_mdio"; + am->mii_bus->read = ipq40xx_mdio_read; + am->mii_bus->write = ipq40xx_mdio_write; + am->mii_bus->priv = am; + am->mii_bus->parent = &pdev->dev; + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); + + am->dev = &pdev->dev; + platform_set_drvdata(pdev, am); + + return of_mdiobus_register(am->mii_bus, pdev->dev.of_node); +} + +static int ipq40xx_mdio_remove(struct platform_device *pdev) +{ + struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev); + + mdiobus_unregister(am->mii_bus); + + return 0; +} + +static const struct of_device_id ipq40xx_mdio_dt_ids[] = { + { .compatible = "qcom,ipq40xx-mdio" }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids); + +static struct platform_driver ipq40xx_mdio_driver = { + .probe = ipq40xx_mdio_probe, + .remove = ipq40xx_mdio_remove, + .driver = { + .name = "ipq40xx-mdio", + .of_match_table = ipq40xx_mdio_dt_ids, + }, +}; + +module_platform_driver(ipq40xx_mdio_driver); + +MODULE_DESCRIPTION("IPQ40XX MDIO interface driver"); +MODULE_AUTHOR("Qualcomm Atheros"); +MODULE_LICENSE("Dual BSD/GPL");